SU1233213A2 - Dynamic internal storage - Google Patents

Abstract

The invention relates to the field of computing technology, in particular, to storage devices of dynamic type, and can be used in digital computers, data acquisition and processing systems, information display systems. The aim of the invention is to increase the reliability of the device. The device contains a memory block and a regeneration controller that contains a key, element 2 IZHE, a pulse generator, a trigger, a timer and a counter. The regeneration controller provides a regenerative dynamic storage device in cases when the frequency of calls is lower than acceptable. I zp f-ly, 2 ill. you 00 00 ND 14)

Description

one

The invention relates to computing techniques, in particular, to dynamic memory storage devices, can be used in various digital computers, data acquisition and processing systems, information display systems and is an improvement on the device. main auth. W 1019493,

The purpose of the invention is to increase the reliability of the device.

FIG. 1 shows a block diagram of the device according to the invention; FIG. 2 is a regeneration controller block diagram and an example of a specific timer implementation. .

The device contains a dynamic storage device (DZU) 1 and the controller 2 regeneration. Regeneration controller 2 sod, ep} kit electronic key 3, element 2IL-HE 4, generator 5 pulses, trigger 6, timer 7 and counter 8, Timer 7 is a voltage comparator whose output is a timer output . The inverter’s input of the comparator is supplied with a threshold voltage from a resistive voltage divider 9, and the direct input is an exponentially increasing voltage from the middle point of a series-connected RC circuit, the output of the resistor with which is connected to the power supply 10, and the output of the capacitor 11 - to common wire. The middle point of this RC circuit is connected, in addition, to the collector of the key transistor 12, the emitter of which is connected to the common wire, and the base through the limiting resistor 13 to the output of element 2OR-HE 4,

Logic elements of integrated circuits, for example, 564 series, Electronic key 3 can be easily implemented on the keys of the same series, Hanpimep 564CTZ, as an element 2ILI – HE 4, trigger 6, counter 8, oscillator 5, Hanpimep 564CTZ can be used as timer KP1006BI1 or it can be implemented using discrete elements and a voltage comparator, for example, 521 SAZ. The device works as follows.

With a frequency of circulation satisfying the regeneration condition, i.e. ne

2332132

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The circulation period is MN times less than the regeneration period (M is the number of storage lines, for example, 128 for 565 RUH | N is the number of storage groups) under the condition of access to this memory or the circulation time is M times less than the regeneration period , the pulses of circulation pass through the element 2Ш1И-НЕ 4, open the timer transistor, the capacitor of the RC circuit periodically discharges and the voltage on it does not exceed the threshold, thus, timer 7 does not generate a pulse of setting trigger 13, 6 and signal from the direct output

the trigger 6 sets the key 3 to the state in which the circulation pulses arrive at the DZU, and the regeneration and access to the DZU I is performed in the same manner as in the Ex-Thiv device, the Inverse signal from the output 6 holds the i-th counter 8 in the left state.

When the processor is stopped or in cases when the frequency of the arrival of circulation signals is less than the required dp regeneration, the capacitor of timer 7 has time to charge up to poroBoi o voltage, and when the threshold voltage is exceeded, the timer comparator generates a signal. the trigger: th trigger b to the state corresponding to the passage of pulses

from the generator 5 through the key 3 to the DZU I and the counting input of the counter 8, which in this case starts counting, since the signal from the inverse output of the trigger 6 enables the counting. Upon enrolment

to the input of the counter 8 the required number of pulses (the number of pulses is equal to the number of rows at all; the DZU drive with the maximum number of rows) the signal from the output of the counter 8 resets the trigger 6

P,. passage through element 2IZH-NN; 4 to timer 7, it transfers it to its original state: it is broken across capacitor I through resistor 2. Key 3 is overloaded and allows to pass;

DZU 1 of the reference signals, and the inverse signal from the exit of trigger 6 prohibits the counting by the counter 8

Takkg-; Thus, the regeneration controller provides the regeneration of the DZU I in pejKi-gmahma shutdown in cases when the frequency of curing is lower than the allowable one, which increases the reliability of the device.

Claims (2)

Invention Formula 1, Dynamic random access memory by auth.St. No. 1019493, characterized in that, in order to increase reliability, it comprises a regeneration controller consisting of element 2ILYE, pulse generator, trigger, counter, timer and key, the first input of which is the device access input and connected to the first input element 2ShSh-NOT, the second key input is connected to the output of the pulse generator, and the control key input is connected to the forward output of the trigger, the installation input of which is connected to the output of the timer, whose input is connected to the output of the element 2Sh1I-NOT, the second input of which to the reset input of the flip-flop and the output of the counter, the count input of which is connected to the output of the key and is the output of the controller regeneration, the reset input of the counter is connected to the inverse output of the trigger. 2. A device according to claim 1, characterized in that the timer contains a voltage comparator, the output of which is the timer output, the source of the threshold voltage on a resistive voltage divider to which the voltage comparator inverted input is connected, the direct input to the voltage comparator the middle point of the differential chain, one of the outputs of which is connected to the power source, and the other to the common bus, the middle point of the differential chain is connected to the collector of the key transistor, the emitter of which is connected to the common transistor, and the base - with one output of a limiting resistor, the other output of which is a timer input. 0t / IZ.l .2 Editor O. Bugir Compiled by V. Gordonov Tehred I.Gaydosh Proofreader M.Maksimishinets Order 2777/54 Edition 543 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5  ----------- ... Production and printing company, Uzhgorod, st. Project, 4