SU1226479A1 - Device for connecting input-output equipment with multisegment bus - Google Patents

Abstract

The invention relates to the field of computing and can be. used to connect input-output devices (I / V) to a multi-segment backbone of control computing systems with sequential arbitration. delays caused by the expansion of the highway. An interrupt enable signal switching unit is inserted into the device, which allows the priority block to be placed not in the beginning of the segment, but in its middle. The interrupt request signals from the capture blocks, located on the right and left of the priority block, are entered into it separately through a block of gates. The interrupt enable signals, the source of which is a priority block, are sent to a switching unit, which, depending on the bus condition of the interrupt requests, transmits them either to the right or to the left side of the capture units. Within each group of capture blocks, the transmission enable signal is propagated sequentially. 1 hp ff, 9 ill. sl to tc sh with

Description

The invention relates to computing and can be used to connect input-output devices (UVE) to a multi-segment backbone of control computing systems with sequential arbitration.

The purpose of the invention is to increase the throughput of the multi-segment trunk by reducing the time of arbitration, the access time of the air-blast connected to the non-processor level to the system resources, and reducing the delays introduced when expanding the scientific research institute of the trunk,

Fig, 1 shows a block diagram of the device; Figures 2 and 3 are functional diagrams of an interrupt enable signal switching unit and a priority block; 4 and 5 are the timing diagram and the block diagram of the operation of the priority block; FIGS. 6-8 are a functional diagram, a timing diagram and a flowchart of the algorithm for the operation of the highway capture unit; figure 9 is an example of a multi-segment highway using the proposed device.

The device (Fig. 1) contains a priority block, the first information control bus 2 of the trunk, blocks 3 and 4 of the capture of the highway of the first and second groups, the second information control bus of the highway 5, the processor 6, the input-output device 7, the first and second buses 8 and 9 of the interrupt requests, the first and second buses 10 and 11 of the interrupt permissions, the interrupt enable signal switching unit 12, the block of 13 OR elements, the bus 14 and 15 interrupt requests and permissions.

Block 12 (figure 2) contains the element OR 16, the register 17, the delay element 18 and the first 19 and second 20 groups of elements AND,

Block 1 (FIG. 3) contains the register 2 interrupt requests, the control input 22 of the register 21, the decoder 23, the second bus 24 of the decoder 23, the elements AND 25, the comparison circuit 26, the first group of inputs 27 of the circuit 26, the element 28, the line 29 signals Sample acknowledgment, trigger 30, element 31, second signal line 32 interrupt, input bus 33 data elements 34 and 35, delay elements 36, trigger 37, register 38, executor synchronization signal line 39, break input line 40 interrupt, data output bus 41 and reset line 42.

Block 3 (4) (Fig. 6) contains triggers 43 and 44, signal line 45 Interrupt request element AND 46, element OR NOT 47, element AND 48, signal line 49 Sample confirmation,

elements AND-NOT 50, element AND 51, elements 52 of delay, elements AND 53, signal line 54 Zan then, element 55, element AND-NOT 56, elements AND-NOT 57, typesetting field 58 of the vector

interrupt, data bus 59, synchronization signal of the executor, signal interrupt line 61, AND-NOT element 62, OR-NOT 63 element and AND-64 element.

The device works as follows

In contrast to the known in the proposed device, block 1 is located not at the beginning of the segment, but in its

the middle (fig, 1). This is achieved by introducing block 12, block 13 and changing the nature of the connection of block 1 to the request and interrupt bus lines.

In a device for organizing parallel operation of a high-performance processor 6 with devices. 7 uses a multi-level interrupt system. As the device 7 can be used as slow-acting input-output devices, prohibiting the interruption of the processor 6 to process information in their registers, and

high speed; off-processor devices requesting unit 1 to use bus 2. If device 7 had the need to interrupt the processor, then

it initiates the operation of the corresponding block 3 or 4, the first group of blocks 3 requests an interruption, forming a high level on the bus 9, and the second group of blocks 4 - on the second

bus 8. Interrupt requests from the first and second groups of blocks 3 and 4, connected to the appropriate priority level, are combined by block 13, and via bus 14 go to block 1, which passes their arbitration — the selection of the highest priority level. The arbitration process begins with a high-level synchronization signal driven by bus 5 from processor 6. As a result of the arbitration on one of the bus lines 15 corresponding to the highest priority request received, in block 1 there is a high level that goes to block 12. In each cycle Arbitration high level in the bus 15 can be only on one of the lines corresponding to the most priority request.

The purpose of block 12 is the transmission of the interrupt enable signal from the bus 15 to either the first 10 or the second 11 interrupt enable bus. The appearance of a high level on bus 15 is the result of the response of block 1 to an interrupt request received from either a group of 3 blocks, or a group of 4 blocks, or from both groups simultaneously. The information input of block 12 is connected to bus 9. This method of connecting block 12 means that the priority of blocks 4 is higher than the priority of blocks 3 connected to the same system level. Therefore, if there is a high level on the corresponding line of the second interrupt request bus (there is a request from the second group of capture blocks), the interrupt enable signal will be transmitted to bus 11.

A sufficiently large (in the architectural sense, unlimited) number of capture units can be connected to each system priority level. In order for the priority block (meaning the known device or the switching unit in the proposed) to select from the group of requesting capture blocks connected to a given priority level, the capture block having the highest priority at this priority level, unidirectional buses 10 and 11 are inserted into the system, the number of which is equal to the number of priority levels. These buses sequentially pass through all the grip blocks connected to this priority level, and the closer to block 12 there is a block 3 or 4 in the electrical circuit, the higher priority at this level it has.

The high signal level on bus 11 (if there is a request from blocks 4) is fed to the input of the first block 4 from the second group, in which it is analyzed. If the device is 7,

associated with this capture unit, is not a signal source on bus 9, then a high level is transmitted to the continuation of bus 9 to the input of the next block in this group. And so on until it reaches the capture block that requests the interrupt. The requesting unit 4 prohibits further signal transmission through the bus 11

and responds to block 1 by forming a low LEVEL signal Confirming a sample on bus 2, in response to which block 1 resets the signal on bus 15 (sets low),

which causes a reset on bus 11 by block 12.

In the system under consideration, the principle of communication between devices is asynchronous. Only two devices can exchange at a time in the system. One device controls the transmission of information through the system backbone and is the master (master), the other device involved in this transfer becomes the actuator (performer). Each master, when working with the contractor, forms on the corresponding line of the bus 12 a signal

system devices that the system trunk is occupied. When the setter finishes the exchange of information with the performer, he resets the Zagshto signal and one of the devices in the system that has

the highest priority at any given time, among other devices that require a system trunk, becomes a master. The selected device, which as a result

The arbitration has generated a signal. The sample acknowledgment is a future driver, which will become such after the release of the bus 12 by the current driver.

The capture unit - master - forms its own signal on the first information bus; Zan then, resets the signal. Sample acknowledgment, sends information to the data bus, uniquely

the determining block, the capture is the source of the interrupt, and strobing it with a synchronization signal Interrupt. Block 1, having received the Interrupt signal, produces a time sufficient to terminate transients in bus 2, receives data and responds to the master with a synchronization signal Synchronization from the agent. The capture unit - setting device 4, receiving the synchronization signal of the executor via bus 2, removes information from the data bus, resets the interrupt signal and releases bus 2 for other-5 bus 9). Therefore, the corresponding triggering gears, remove the low signal level Zan then. Block 1, receiving a reset signal Interrupt, resets the synchronization signal of the performer

and the system returns to its original state.

In the initial state of block 12 (FIG. 2) there are no signals at the inputs of the element OR 16 — low levels are kept by block 1 on bus 12. Accordingly, there are no signals at the outputs of the first and second groups of elements I. The state of the inputs 9 of the register 17 is indifferent.

Suppose that one of block 4 requires system resources, forming a high signal level on bus 9. Block 1 performs arbitration, and if conditions allow, generates a signal on the corresponding bus line 15 that goes to the input of the OR circuit 16 and the first inputs of the corresponding pair of elements are 19 and 20. The pair of elements is an elementary switch and their number is equal to the number of priority levels in the system.

The purpose of elementary switches is to switch the signal from bus 15 to bus 10 or 11. At each time point, block 1 generates a signal to allow no signal only on one of the bus lines 15, therefore in blocks 19 and 20 only one of the elementary switches will be ready for operation . The high level from the output of the element OR 16 is fed to the input of the element 18 and records the information in the register 17.

After some time being processed by element 18, a high level appears at the second inputs of the elements in blocks 19 and 20, allowing the analysis of the state of the register 17 trigger, which is connected to the inputs of the previously prepared elementary switch. If this trigger is set to the logical 1 state, then the Enable interrupt signal is transmitted to the bus 11.

Suppose that the source of the interrupt request signal received in block 1 is one of blocks 3. In this case, at the time of writing to the register 17, the logical line O is stored on the corresponding line of its input information bus 9 (no interrupt requests

0

five

0 5 0

h 0

50

The germ of register 17 is set to the logical O state, and in this case, the Enable interrupt signal will be transmitted to the corresponding line 10. The number of lines in the corresponding buses of block 12, register size 17, the number of elements in blocks 19 and 20 elements are equal to the number of priority levels in the proposed device.

In block 1 (FIGS. 3-5), the triggers 30, 37, and 38 to the register 21 in the initial state are cleared.

The bus 14 signals are fed to the inputs of the register 21, With the arrival of the interrogation signal interrogation signal on line 22 from the processor 6, the state of the bus 14 is fixed in the register 21, the outputs of which are connected to the decoder 23, which is the selection of the most priority request and performed on the AND elements -NOT.

At one of the outputs of the decoder 23, -.the corresponding highest priority request on the bus 14 at this time point, a low level is formed (logical 1). The first group of inputs of the comparison circuit 26 receives information from the bus 5 states of the bits of the register of commands and processor states, in which the program priority is recorded, is performed at the current time. The comparison circuit 26 compares the processor priority with the highest bus request 14. If priority of the processor is lower than the priority of the requesting unit 3 or 4, a high level is generated at the output of the comparison circuit 26, which is fed to the first input of the circuit: AND 28. In the absence of a signal Confirmation of the sample in line 29 at the output element E28. A high level appears, which enters the inputs of the elements E25 and the trigger 30. As a result, the trigger 30 changes to the state, logical 1, and at one of the outputs of the E25 elements corresponding to the highest priority request, high level that enters the tire 15.

The capture unit - the source of the corresponding interrupt request signal on bus 8 or 9 in response to the arrival of a signal on bus 10 or 11 generates a signal in line 29 A sample acknowledgment that results in a high level And 31 at the output. As a result, the register 21 goes to the initial state, and the signal on the bus 15 is reset.

When the pickup unit is the source of the request, it becomes a master in the system, it generates an Interrupt (line 32) signal on bus 2 and information on the bus 33. The signal on line 32 goes to the first inputs of And 34 and 35 elements and through the time it takes for delay element 36 to work. a high level arrives at the control inputs of the trigger 37 and register 38. The trigger 37 generates the arrival of the Interrupt signal via line 32, and the register 38 stores the contents of the data lines 33 on bus 2. Block 3 or 4 is the preset. Chip on lines 33, transmits information that uniquely identifies the device - the source of the interrupt. The time delay by delay element 36 is necessary to complete the transients in bus 2 and write reliable information to register 38. A high level of trigger 37 triggers a reset of trigger 30 and the formation of a sync signal in LINE 39 bus 2

qi from the performer. After resetting the signal on line 32, the signal on line 39 is also reset. At this point the arbitration procedure and the interrupt operation in the trunk end.

Information about the fact of the interruption (line 40) and the source of the interrupt (line 41) enters the processor, which, after processing it, resets the flip-flop 37 and the register 38 with a signal on the line 42, and the circuit returns to its original state.

In the initial state, the triggers 43 and 44 of block 3 (4) are reset. Block 3 (4) starts up when a high level signal appears in line 45, which originates from device 7. In device 7, the need to form a signal in line 45 arises when completing operations that were previously started by the processor (or when errors as a result of their implementation). Device 7 interrupts the processor to process the latest information in its registers.

The high level of the signal in line 45 leads to the formation of a high level at the output of the element I 46 - at bus 8 or 9. Coming from high level block 12 over bus 10 or 11 sets the trigger 43, a high level from whose output goes to the first input of the element OR-NOT 47, which causes a signal reset on bus 8 (9), to the input of the element AND-NOT 48, which causes the formation of a signal in line 49 to confirm the sample, and to the first input of the element AND-NOT 50, resulting in its output appears low. This low level arrives at the first input of the And 51 element and confirms the low level at its output, and after the time that the delay element 52 performs, a high level appears at the second input of the And 51 element. The interrupt enable signal on bus 10 or 11 is the source The block is block 12; it passes through all blocks 3 (4) connected to this priority level in succession. This signal, received at the input of the first block 3 or 4, is analyzed and, in the event of a service request, it is given the right to use the system's resources (the case in question), otherwise the signal 10 or 11 goes to its continuation (output of the And 51 element).

Block 1 in response to the signal Confirming the sample on line 49 resets the signal on bus 10 or 11. Element 53 monitors the release of the bus by the previous setter (low reset — on line 54 the busy signal and reset the signal on bus 10 or 11 by block 12. When these conditions coincide, the output level of the element 53 forms a high level, and the trigger 44 goes into the logical 1 state. As a result, the sample acknowledgment signal on line 49 is reset, the Occupation signal in line 54 is set, and the device becomes a setting device. mom out the element 55 and goes to the inputs of the element 56 and elements AND-57, the input field of the interrupt vector 58 is connected to the other inputs of the interrupt vector 58 — the block identifier 3 (4). The presence of a jumper in this bit 58 corresponds to the logical O and vice versa the jumpers are logical 1. The interrupt vector along lines 59 goes to block 1. When the Sync signal is reset, the synchronization from the previous or 4 th

The unit 3 generates an interrupt vector with an interrupt signal in line 61. Block 1 responds with a synchronization signal from the executors in line 60, under the action of which a high level is generated at the output of the AND 62 element, and a low level at the output of the OR 63 element and the trigger 43 goes to the initial state. As a result, the signals in the lines 5 59 and 61 are reset, which is the end of the Interrupt operation in the system trunk. Block 3 or 4 is in an intermediate state (trigger 44 is cocked), in which the sinal signals on buses 8 or 8 and 2 are not formed, and the signals on bus 10 or 11 are transmitted through block 3 or 4, its state changes (due to the AND element). 64). The transfer of block 3 or 4 to the initial state can be made only after the signal is reset on line 45 by device 7.

A device with a single-segment trunk (Fig. 1) allows organizing the operation of a certain number of capture units. A highway within the load capacity of the source elements of signals in the trunk buses and within the possible geometric length of the highway. If the number of capture blocks interrupts the capabilities of the load capacity of the elements AND / OR, their arrangement requires a large geometric length, then it is possible to use a device with a multi-segment trunk. In each additional segment, there is also an I priority block 1, which is located in the middle of the segment.

In blocks 1 of additional segments, in addition to the nodes that perform the arbitration itself, there are nodes that relay (transmit signals without inversion with a preliminary effort) signals between the information control buses.

 Fig. 9 shows an example of a device with a multi-segment trunk (input-output devices 7 not associated with the corresponding blocks 3 and 4, and processor 6 are not shown. In addition, in each segment instead of blocks of OR elements, block 1 of priority and block 12 and their interconnections in accordance with FIG. 1 shows block 65).

In addition to input / output devices, computers requesting a processor to programmatically process information in their registers can use devices capable of transmitting information without using a processor, called direct memory access devices. In order for the system trunk to be placed at their disposal, these devices request not to interrupt the operation of the processor, but to suspend it. Direct access devices are critical to latency.

providing the system backbone, as they may lose information prepared for transmission. These include fast synchronous devices such as magnetic disks, drums and other devices. properties. The need to satisfy the fast service requirement of critical devices forces computer developers to introduce a separate priority level into the system, the so-called direct access level. The arbitration mechanism among the devices connected to the direct access level is similar to the arbitration of the processor interrupts. . In a layered device, the direct access level is the highest. However, if a direct access request came to the priority block after the start of the interrupt arbitration cycle, direct access arbitration can be started only after the completion of this cycle.

Formula of invention

Claims (2)

1. A device for connecting I / O devices to a multi-segment trunk, containing two groups of trunk acquisition blocks and a priority block, whose synchronization input is connected to the information capture and control inputs of the first and second groups via the first information and control bus of the trunk; the interrupt request inputs of which are connected to the interrogation outputs of the corresponding I / O devices, the interrupt enable output of the irro trap block of each group (i M-1) connecting It is provided with an interrupt enable input i + 1 of the line capture unit of the same group, characterized in that, in order to increase the capacity of the multi-segment trunk, the OR element block and the interrupt enable signal switch are entered into the device, and the OR block group of the OR block element is connected a group of inputs of requests of the priority block, the information and control input-output of which is connected via the second information and control bus of the trunk to the input-output of the processor, and the group of resolution outputs - from the group kitsih control signal switching unit inputs the interrupt enable, first and second outputs of which are connected respectively to the enable input of the first line capture unit of the first and second groups, and the group of information inputs - outputs an interrupt request with a capture line of the second group of blocks and the first group of inputs of the block of elements OR, the second group of inputs of which is connected to the outputs of the interrupt request requests of the trunk acquisition blocks of the first group. 2. The device according to claim 1, of which is that the switching unit of the interrupt enable signals contains a register, the group of information inputs of which is a group of information inputs of the block, two groups of AND elements, the first inputs of which are connected respectively with groups of inverse and direct outputs of the register, second inputs - with a group of control inputs of the block and a group of inputs of the OR element, the output of which is connected to the synchronizing the register input and through the delay element to the third inputs of the AND elements of the first and second groups, the outputs of which are respectively the first and second outputs of the block. Fy 1226479 6 T 60 61 Installed by Itiunopa npeptilOHUf on ft / ia-, dtlS7} Starter fuenajiA fS4), 3Ctni oui: inet-ja aomuiat, cfpac cut- PM (49) t. Figv Editor N. Yatsola Compiled by V. Vertlib Tehred L.Oleynik Proofreader S.Shekmar Order 2136/50 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4