SU1226338A1 - Apparatus for phase-meter calibration test - Google Patents

Abstract

The invention relates to radio measurements and can be used to calibrate phase meters in the low-frequency and low-frequency ranges. The purpose of the invention is to simplify the device and software management. The device contains a master oscillator 1, a counter 2, a switch 3, operative storage elements 4 and 5 serially connected in both channels, registers 6 and 7. Digital-analogue-soft converters 8 and 9, attenuators 10 and 11, signal attenuation code registers 12 and 13, recorder 14 frequency code, computing unit 15, control unit 16, tires 17, 18 and 19. 3 sludge. o to O5 00 WITH oo Fig, 1

Description

The invention relates to electron radio measurements and can be used to calibrate phase meters; low-frequency and infra-low frequency ranges

The aim of the invention is to simplify the device and allow a lot of software control.

On fn.1 shows a block diagram of the device; in fig. 2 and 3 - structural schemes of possible implementation options for the computing unit and the control unit.

The device (Fig. 1) contains successively connected frequency set-1DIY generator 1, counter 2 and switch 3 connected in series 3 of both channels with operative storage elements 4 (5), registers 6 (7), digital-to-analog converters 8 (9) and attenuators 10 (11), with registers 12 (1.3) connected to them, attenuation signal, frequency code register 14, connected to frequency generator 1, the output of which is connected to control inputs of registers 6 and 7 of both channels, computing unit 15 and control unit 16 which are connected to each other. Another bi-directional bus 17 of control signals, address bus 18 and a bi-directional data bus 19, to which the information inputs of the operative storage elements 4 and 5, registers 12 and 13 of the attenuation code and the frequency code register 14 are also connected, are connected to corresponding outputs of the control unit 16, also connected to the control input of the switch 3, the second information input of which is connected to the address 18 bus of the output - to the combined address inputs of the operative memories Etoch 1; 1x of the electronic components 4 and 5.

Computing unit 15 (Fig, 2) contains a microprocessor module

20, permanent storage element

21, the decoder 22 and the operative storage element 23, the address outputs of the microprocessor module 20 are connected to the address inputs of the constant 21 and the operation 23 storage elements 5 of the inputs of the decoder 22. And the bus 18 of the device address information inputs-outputs of the microprocessor . of mine mine 20 are connected to

information inputs / outputs of the operative storage element 23 and outputs of the permanent storage element 21, which are connected by control inputs to the outputs of the decoder 22 and outputs Record, Read microprocessor module 20, the control outputs of the control signals of which are connected to the bus 17 Guiding signals devices.

The control unit 16 (FIG. 3) contains a decoder 24, the outputs of which are connected to the block of elements AND 25 (elements 25-1-25-8), the element OR 2 FlS-TpHrrep 27, the element 28 reset, connected by the output to the first input the OR element 26, the second input of which is connected to the output of the element 25-8, and the output with the R input of the RS flip-flop 27, S is the input of which is connected to the output of the AND element 25-7, the control unit also includes the display element 29 and control panel 30, register 31 and driver 29 are connected with each other, while the control input of the display element 29 is connected to the output of element 2 5-1, and its information inputs and outputs of the bits of the register 31 are connected to the device data bus 19, the inputs of the decoder 24 are connected to the device address bus 18., the outputs of the driver 32, the reset element 28, the register entry input 31 and the second inputs of the AND 25 elements connected to the bus 17 control: device signals.

The device works as follows.

In fleas 16 controls, parameters are entered that determine the number of spectral components, the values of their amplitudes, frequencies and phases in the generated output signals. This information is entered into the computing unit 15 via the data bus 19, which determines the necessary frequency of the frequency generator 1 and attenuation coefficients of attenuators 10 and 11 and writes the corresponding control codes in the frequency code register 14 and the code registers 12 and 13 frequency reduction.

Further, on command from the computing unit 15, the control unit 16 generates a control signal for the switch 3, which connects the address inputs of the operative storage elements 4 and 5 to the bus 18 of address 3

numeral block 15. In computation block 15, output signal samples are formed, which are alternately recorded on the data bus 19 into operative storage elements 4 and 5. The number of signal samples per period (N) and their size determine the amount of memory selected based on the required the accuracy of the phase shift. The minimum discreteness of the phase change does not depend on the number of addressable memory cells and is determined by the size of the operational storage elements 4 and 5, registers 6 and 7, and digital-analog converters 8 and 9.

Upon completion of the recording, the control unit 16 transfers the operative storage elements 4 and 5 to the read mode and connects their address inputs to the output bits of the counter 2 through the switch 3. The current counter code 2 with the volume N determines the address of the sequentially read cells of the operative storage elements 4 and 5, The content of which, according to the signal of the frequency-generating generator 1, is recorded in the register 6 (7) of the corresponding channel and then using the DAC 8 and 9 is converted into analog signals fed through attenuators 10 and 11 to the outputs of the device. The amplitude h phase spectrum of these signals corresponds to the initial parameters entered into the computing unit 15.

When one of the signal parameters is changed in the control unit 16, a control signal is generated, which arrives at the computing unit 15 via the control signal bus 17, through which all the described preparatory operations are performed and one or both of the operational storage elements 4 and 5 are overwritten.

The structure of the computing unit 15 and the control unit 16 depends on the base element used. The most promising implementation of the computing unit 15 is based on a microprocessor. A typical block diagram of a microprocessor-computing unit with a minimum configuration is shown in FIG.

In the permanent memory element 21, programs and constants are stored in the operational memory element 263384

At the moment 23, the current information, the selection of the corresponding element is carried out according to the signals of the decoder 22. The microprocessor module 20 performs the processing and exchange of information and is connected with the device by a system of address (address bus 18), information (data bus 19) and control buses (bus 17 control signals 10). Control signal bus 17 may include write, input, output (output), and interrupt and reset (input) signals. The control unit 16 (FIG. 3) performs the functions of generating control signals necessary for organizing the exchange of information between the computing unit 15 and devices external thereto, and also the input of information from the control panel and visual control (indication) input data and data from the computing unit 15..

The read (write) signals to the operative storage elements 4 and 5, registers 12 and 13 of the attenuation code and the frequency code register 14 are generated by decoding the address code of the corresponding element d (decoder 24) and conjugating its output signals with the write, output signals from the ultrasonic unit 15 (the block of elements And 25).

Similarly, two signals are formed at the outputs of the electrons 25-7 and 25-8 that control the RS flip-flop 27, the output of which determines the direction of information transfer through the switch 3. With the help of the reset element 28, the computational unit 15 and the RS flip-flop 27 are initially set .

Register 31 stores information about the signal parameters and the mode of operation of the device, inputted from the control panel 30. On a Signal Input, this information is entered into the computing unit 15. The information is entered either when the device is initialized (by the Reset signal) or when the keyboard state of the control panel 30 is changed, causing the formation of an interrupt request signal (driver 32) to the computing unit 15 .

five

0

The parameters of the generated signal and data on the operating mode of the device can be output from the computational

unit 15 via bus 19 data to the element 29 of the display (display). The signal to access it is formed by the element AND 25-b

The change in the parameters of the signals can also be realized by the program g previously recorded in the computing unit 15 or entered into it from the control panel 30.

The integrated circuits of the HivjeroT RAM are highly integrated, and the calculation: the slip unit is quite simply implemented on the basis of microprocessor-based LSIs. As a result of the elimination of a large number of ROMs, DACs, and accumulators that have a small degree of integration, the amount of hardware is significantly reduced - a controlled computing unit makes the device functionally flexible, allows, in contrast to the well-known, to change its parameters and algorithm without changing its structure. In addition, the discretization of the phase shift change does not depend on the number of addressable cells, pn ~ 1 t, which reduces the requirements on its volume.

Claims (1)

Invention Formula A phase meter calibration instrument containing a digital-to-analog converter and an attenuator connected in series in the first and second channels, as well as five A master oscillator connected to the register entry inputs, characterized in that, in order to simplify the device and enable programmatic control, a frequency code register, a counter, a switch, two operational keys are entered into it: a signal, a control unit and a computing unit connected to a control unit of a bidirectional bus of control signals, an address node and a bidirectional data bus, to which informational inputs of the signal of the signal attenuation code are also connected the operating, operative paging elements and the frequency code register; the recording inputs of which, as well as the control inputs of the switch, are connected to the corresponding outputs of the control unit; the outputs of the operational storage elements are connected to the information inputs of the registers of the first and second channels, respectively; the address inputs of the operational storage elements are combined and connected through a switch with the outputs of the bits of the counter and the bus a, the cres of the computing unit, the input of the counter is connected to the output of the frequency coding generator , the outputs of the frequency code registers and the signal degradation code are connected respectively to the frequency control, and a generator and attenuator of the first and second channels, the outputs of which are connected to the device outputs. / -  AL SHL sh l l MUST7 .З