SU1224792A1 - Device for generating signals for correcting kinematic errors - Google Patents

Abstract

The invention relates to the field of software control of machines and is intended to generate correction signals to compensate for systematic errors in the position of the machine end units caused, for example, by kinematic errors of gears, etc. The purpose of the invention is to simplify the device while maintaining its accuracy. The signal of the current position, depending on the direction of movement, is fed to the buses + i or - i. In this case, the signals are fed to the counter input, changing its state and the coded signal at its output, each of which corresponds to a certain position of the machine organ. With the equality of the current and stored in the decoder of the positions of the codes, one of the outputs of the position decoder receives a signal to one of the memory bus lines. When this happens, the register and trigger of the memory block are reset, and then the encoded speed signal is written to the register and the sign is written to the trigger. At this point (with a write pulse) the first counter-divider is in the zero position. The first pulse -i through the first element AND of the first switch gates the recording of the code from the register of the memory block to the first divider counter and resets the second divider counter to O. Then this pulse passes through the sign switch to the + L output of the device. The following pulses on the bus -f through the first switch will be subtracted from the contents of the first divider counter and summed up in the second counter-. divider When reaching zero in the first counter-divider, the next pulse through the second switch will again go to the second AND element and ensure that the speed code is written from the memory block and the code is reset in the shared divider counter. In this case, a corrective impulse is formed, which through the sign switch will arrive at the output of the device. 3 hp f-ly, 5 pcs. about (L to IsD 4iib WITH to

Description

The invention relates to software control of machines and is intended to generate correction signals to compensate for systematic errors in the position of the final links of the machine caused, for example, by kinematic errors of transmission, misalignment of connections and systematic error of position sensors,

The aim of the invention is to simplify the device while maintaining its accuracy.

FIG. 1 is a block diagram of the deviceJ in FIG. 2 - functional schemes of the decoder and the memory block; FIG. 3 is a diagram of a sign komgutator; in fig. 4 shows an example of the formation of an approximate systematic error signal in FIG. 5a is a more detailed example of the formation of an approximate systematic error signal; in fig. 56 is a time diagram of the operation of the device.

The device contains a counter of position 1 (FIG. 1), a decoder 2, a memory block 3, the first 4 and second 5 elements And, the first 6 and second 7 counters-dividers, the driver 8 of the pulse 9 coBj STATE1DY from the first 9 and second 10 delay elements, the first 11 and the second 12 pulse switches, the device also contains a commator 13 characters, the decoder 2 includes elements AND-OR 14 ,, 142 - .. 14, elements 2И-1-ШИ 15, , 152 ... 15) (, impuls formers (16 and 17. Block 3 contains pulse generator 18, group of elements OR 19, elements I.ГШ 20, 21, register 22, trigger 23 Switch 13 characters consists of the element IL 24, elements AND 25 to 26.

FIG. 1 are designated - f j, + {, - bus input pulsesJ in FIG. 2 - sign is the sign output of memory block 5

in fig. 4 and 5 - OC is a systematic error signal, 5 is a systematic error, tf is the position of the drive, b sections with a constant rate of change of the error D ,, 2, ... ip, are displacement signals corresponding to a single correction pulse, a reverse point.

The t, 6 and 7 counters are a1 with reversible. The delay time of elements 9 and 10 is chosen not less than the time of transient processes in elaments 1-3 and not longer than the period of the maximum frequency to 4 pulses.

S

4 0

S ji ..

-S

at inputs 4 or -1. And when the counter 6 is located (or the counter 7; in the zero state at its output, the signal appears zero (R is the fault inputs of the counters).

Switch sign 13 operates as follows. At a high signal level; 1la at the control input of the sign switch, signals from the information inputs arrive at the output - A, and at a low signal level - at - U.

The preparation of the device for operation is carried out as follows. A systematic error signal, e.g., the kinematic error of the machine transmission or the position measurement error, is preliminarily measured and recorded. According to the obtained record, an approximate signal is formed corresponding to the signal of systematic error S (Fig. 4) with respect to a given or current position of the cf drive. O signals; make up sections b at a constant rate of change of error. They remember the positions cf, -cf of the drive, which correspond to the boundaries of the segments t. For comparison, in FIG. Figure 4 also shows the positions of the avg. -P water corresponding to the boundaries of the sections constituting the approximate signal generated by the prototype device. Memorizing the cf, -Lf7 positions for each particular machine in the decoder 2, for example, by appropriately soldering the direct and inverse inputs of the elements 14j-14 to the outputs of the counter 1. For each Cf position (plot), the speed and sign signal is stored in block 3 correction. This is accomplished, for example, by unplugging the inputs of elements 19 and 20 to the corresponding buses (1 .., k). The formers 16 and 17 serve to increase the reliability of the circuit and provide information from the decoder 2 after the transients are completed in counter 1. Using element 21 and the former 18, the register 22 is reset before the new information is written to it.

 The device works as follows.

The signal of the current position, depending on the direction of movement, is fed to the tires f,. or-in. With

In this case, the signals are fed to the input of counter 1, changing its state and, accordingly, the coded signal at the output. Each coded signal from the output of counter 1 corresponds to a certain position of the machine organ. With the equality of the current and stored in the decoder 2 positions, one of the outputs of the decoder 2 receives a signal to one of the buses (1 ... k) of the memory block 3. When this occurs, the register 22 and the trigger 23 are reset by the input R through elements 21 and 18, and then the encoded speed signal is recorded in the register 22 and the character is triggered 23. The reset is performed by a shortened pulse generated by the former 18 on the forward edge of the pulse 17. The recording is carried out by a pulse from the former 17 after the end of the pulse of the former 18. In the diagram of FIG. 5 shows only the write pulse. At this point, counter 6 is in the zero position. The first impulse -i (it is highlighted in the diagram), delayed by delay element 9, through the first element And of switch 11 performs gating of writing the code from register 22 to counter 6 (Fig. 56, strobe signal. I4 device O 7 ) and reset the counter 7 on the bus Set. About

Then this impulse passes through the switch commutator of the sign to the exit - and devices (d.1). The displacement corresponding to this pulse is conventionally indicated in FIG. 5a. The next pulse on bus -i through switch 11 (second element I) will be subtracted from the contents of counter 6 and summed with in counter 7. When reaching zero in counter 6, the next u1-pulse through the top element And switch again goes to the circuit input element 5 and will ensure the recording of the speed code from block 3 and at the same time ensure the code is reset in the counter 7.

In this case, a correction impulse is formed, which through the switch 13 of the sign arrives at the output D of the device, since the trigger T contains the sign of error +, which is present on the control input of the switch 13 of the sign.

Corrective pulses during the processing of the considered section with a constant speed will appear at the device output after k pulses:

k - h

where h is the increment of the error in units of discreteness.

For this, the speed code written to register 22 will be less than k by one.

At the point Cf, there is a change in the sign of the approximate error signal and the magnitude of the velocity code, since c fj. fixed in decoder 2, similarly at the point Cfg. However, since the signal at the control input of the switch 13 changes, the corrective pulse is detected at the output L.

According to the diagram at the point tp, the displacement is reversed. In this case, the pulses present on bus x are subtracted from counter 7 and summed up in counter 6. If counter 7 is zero (this will be at tfy), a reset pulse of counter 6 is generated and the code of the neighboring section tpg-cf is written to register 22. The point is written to the speed code and the sign of the neighboring (Cfg - (f) section in register 22. Before this, the counter state will be zero and delayed by delay element 10 will reset the counter 6 and write the speed code from register 22 through AND 5 signal strobe And 5 from the output of the first element And comm 12 torus.

It should be noted that when using the device in CNC systems, the signals “« and - and и are summed with the signals + i and i, respectively (not shown).

Claims (3)

1. A device for generating correction signals of kinematic errors, comprising a position counter, a decoder, a first counter-divider, and a pulse shaper, the first output of which is connected to the installation input zero of the first counter-divider, the outputs of the position counter are connected to the group of inputs of the decoder, different that, in order to simplify the device while maintaining its accuracy, it contains a memory block, a second counter-divider, two AND elements and a sign switch connected by a control input with a sign in the memory block which inputs are connected to the outputs of the decoder, and information outputs to information inputs of the first and second elements I, the inputs of which are connected respectively to the second and first outputs of the pulse former and outputs to the information inputs of the first and second divisor counters correspondingly, the first pulse output driver is connected to the first information input k & g / tator of the sign, the second output to the zero input input of the second divider counter and the second information Ion input of the switch of the sign, whose outputs are outputs of the device, the pulse driver by the third output is connected to the subtractive input of the first counter-divider and the summing input of the second counter-divider, the fourth trick - to the summarizing input of the first counter-divider and subtracting input of the second counter The separator, the first and the second inputs of the pulse generator are connected to the pulse inputs of the position counter and the decoder and are the device inputs, and the third and fourth inputs of the pulse generator n dklyucheny vanishing to the outputs of the first and second counters-dividers respectively. 2. The device according to claim 1, characterized in that the pulse shaper comprises two delay elements and the bottom of the switch, each of which consists of two AND elements, the first inputs of the AND elements of the first and second homing switches being connected via the corresponding delay elements respectively, with the first and second inputs of the pulse former, the second inputs of the I elements — with the third and fourth inputs of the pulse emitter, the outputs of the first And elements — with the second and the first outputs of the pulse former, and the outputs of the second I elements — with the third and fourth outputs of the wat ate I1 1pulses. 3. The device according to claim 1, distinguishing and; This is because the memory block contains the group of elements OR, the first and second elements OR, the pulse generator, the register and the trigger, and the elements OR are connected to the buses connected to the inputs of the unit the first element OR is connected to S - the trigger input, the output of which is the output of the memory block, the second element OR output is connected via the pulse shaper to the inputs of the zero setting of the trigger and the register, the information inputs of which are connected to the outputs of the group of the Sh1I elements, and the outputs of the register are connected to ormatsionnym outputs of the memory block. 4 The device according to p. I, about tl and - the fact that the decoder contains elements AND-OR, elements 2I-Sh1I and two pulse shapers and elements of I-SH are connected to the group of inputs of the decoder, the outputs of the elements I-EPI are connected to the first inputs: - 2I-OR elements, the second inputs of which are connected to the output of the first pulse shaper, the third inputs - to the output of the second pulse shaper, the fourth inputs of all elements except the last one are connected to the first inputs: 1 ШХ elements, and the fourth input of the last element 2K-OR Sub-Och The input to the first input of the first element 2И-OR, the outputs of the elements 2И-ИЛ are connected to the outputs of the decoder, the inputs of the pulse formers are connected to the pulse inputs of the decoder. + D .ii S iqn 9 i3 ") four ) - / 3aff. K6CfTTfg. UA- mouth „0 7 cmpoff, L / 5 ijcm ,, 06 rl „Styn H-d-d Compiled by A. Ispraviykova Editor N. Slobod nickname Techred N. Bonkalo Corrector M. Pojo Order 1952/48 Circulation 836 Subscription VPIIPI USSR State Committee on affairs of inventions and otkrysht 113035, MocKBaj Ж-35, Raushsk nab. - ,, d., 4/5 Production and printing company, Uzhgorod, st. Project, 4 t