SU1223377A2 - Device for checking wire communication channels - Google Patents

Abstract

Invention m. used to control and test switchable communication channels. The purpose of the invention is to increase the accuracy of monitoring wired communication channels and increase the reliability of the device. Arrange (L with

Description

The structure contains the 1st master transceiver (PP) 1.1 commands, the 2nd master PP 1.2 commands, the executive PP 2 commands, switches 3, block 4 of the direction of transmission, 1st time analyzer (AVI) 5, 2- The second AVI 6. The second AVI 6 contains the 1st block, 55 comparisons, the 2nd block 56 comparisons, and the element OR 57. Information is exchanged between the master and the executive PP over a communication channel, to a given point of which. The switch is turned on without additional control lines. The following directions can be implemented in the device: a) from the master PP

The invention relates to telecommunications, can be applied to the control and testing of switchable communication channels and is an enhancement of the device according to the basic author. St. No. 1135012.

The purpose of the invention is to increase the depth and increase the reliability of the device.

The drawing shows a structural electrical circuit of the proposed device.

The device for monitoring wired communication channels comprises a first command transceiver K1, a second command transceiver 1.2, an executive command transceiver 2, switches 3, a transmission direction selection unit 4, a first analyzer 5 time slots, a second analyzer 6 time slots. I

Each switch 3 contains logic elements 7-10, a bus of the first information output 11, a bus of the second information output 12, a bus of the first information input 13, a bus of the second information input 14, a bus of control inputs 15-18

The transmission direction selection block 4 comprises the first 19, second 20, third 21 and fourth 22 elements

23377.

1.1 / 1.2 to the executive PP 2 and ia- turn; b) from master software 1.1 / 1.2 to master and executive software 1.2 /

/1.1 and 2; c) from the executive PP 2 to the master PP 1.1 and 1.2. The choice of direction is established by the instructor PP 1.1 /

/1.2. Monitoring is carried out simultaneously with the exchange of information. Since the exchange is performed by even (odd) codes, no prior control is required. The exchange can be made both in parallel and in sequential code. Invention additional to auth. St. No. 1135012, 2C. f-ly, 1 ill.

NOT, first 23, second 24, third 25 and fourth 26 decoders, first 27, second 28, third 29 and fourth 30 elements OR, first 31, second 32, third 33 and fourth 34 elements AND NONE, element OR NOT 35 , fifth element OR 36, element AND 37, bus outputs 38-46 and bus control inputs 47 and 48.,

First analyzer 5 input.

interval contains the adder 49 in the MO-. I have two, a memory block 50, a pulse counter 51, a driver 52, a comparison block 53, and a control output bus 54.

The second time interval analyzer 6 contains the first 55, second 56 comparison units and the element OR 57. The device for monitoring wired communication channels works as follows.

Information is exchanged between the master and executive transceivers via a communication channel, at a given point of which the switch is turned on, without additional control lines.

In the device for monitoring wired communication channels, the following directions can be implemented; from master transceiver about (1.2) to executive receiver

n (M1 power point 2, n and turn; from specifying transceiver 1.1 (1.2) to specifying and executive transceivers 1.2 (1.1) and 2; from executive transceiver 2 to specifying transceivers 1.1 and 1.2,

The direction selection initiative belongs to master transceiver 1.1 (1,2), which implements the choice of the direction of exchange. In addition, the master transceiver 1.1 (1,2) can transfer the initiative to another master transceiver 1.2 (1.1). Monitoring is performed simultaneously with the exchange of information. Since the exchange is performed by even (odd) codes, no prior control is required.

The exchange may be performed in both parallel and serial code. An example implementation is presented for a parallel n-bit code. In the case of using a serial code, only one switched channel line and, consequently, one switch are needed to exchange information.

The essence of the control is that in the switch included in the given point i of the communication channel, the moments of passage of the signal sent from the defining transceiver 1; 1 (1.2) and the signal (confirmation) sent from the executive transceiver 2 or from the defining transceiver 1.2 ( 1.1). At the specified moments, a time interval is formed in the switch, which is compared with the specified inter-

shaft. The predetermined interval is selected from an appropriate ratio.

PL CONTROL area switch - communication channel - executive transceiver 2

O) - and) (ii /,)

Tj 2 (t, - t) +

hti)

const

de tv - the moment of reception of performers

ny transceiver 2 signal;

50

t. - the moment of passage of the switch (set point i of the channel to which the switch is turned on, sent with the signal);

conet ®P signal processing by executive transceiver 2;

five

10 15

20 25

zo .U

five

five

0

3774

i is the point of the wired chile connection to which the switch is connected.

For control of the site, the switch-channel is the master transceiver 1. 2

J ..U) Ul (21 l U - t i + on5l

, C2

where t, is the moment of reception of the signal by the master transceiver 1.2; t is the instant of the passage of the switches by the signal from master transceiver 1.1; onst signal processing time by master transceiver 1.2.

For the control of the area, the switch - the communication channel - the master receiver. transmitter 1.1

W (:) 5 („JJ - and - i + const

( eleven

where ty is the moment of reception of the signal by the master transceiver

with.

t j is the moment when the switch passes the signal from the setting one (1st transceiver 1.2; const signal processing time by the setting transceiver 1.1.

If the time interval formed in the switch is less than the specified one, the channel is healthy, if it is longer, the channel is faulty and automatically turns off. Channel re-activation is performed by master transceiver 1.1 (1.2) by removing and then re-introducing the directional selection signal. In case of failure, the setting transceiver 1.1 (1.2) (processor) can optionally either repeat the monitoring, setting the same direction for the second time, or setting a new direction, or starting the program to start diagnosing the switched channels, issuing, for example, successively to each line of the channel, starting with the first one, the control information (in the absence of it in other bits) and the localization of the failed switchable channel thus.

The device for monitoring wired communication channels operates in three modes. The operation of the direction selection unit 4 occurs in accordance with the functional table given.

In the functional table give

The sequence numbers used in block A of sets (combinations) of logical variables (logical O or A), B, C, and D, characterize the state of the control outputs of the master transceivers 1.1 and 1.2. Each logical variable takes one of two values A a, a, B b, b, C - c, c, d.

In addition, in block 4, the following ratios of the values of logical variables and their physical equivalents are accepted: a b c d g - logical 1 low voltage level (c); a, 1) d - logical O - low voltage level ("5V).

 M4 and F46 are functions of the seventh, eighth and sixth outputs of block 4. Under the function indexes is recorded the one for a given time interval (T ,, T ,,,

ti. ,

T-, y, respectively, V on the formation of which the function gives the resolution (the resolution is given a high level of voltage, which corresponds to the logical O functions F

42

FH "4b)

, F | y, E, g, Fff, and F | g are functions of outputs 15–18 of unit 4, respectively 0

five

0

the function dexes indicate the positions of the logic elements 7-10 of the switches 3, respectively).

Mode 1. In the initial state, the master transceivers 1.1 and 1.2 did not choose directions. On the selection line, there is a high level podufs signal (the values of the logical variables b, D d), Ha outputs 38-44 decoders 23-26 of the transmission direction selection block 4 low level signal.

Let us show, for example, how this signal is formed at the output 42, for which, substituting the specified values of the logical variables in the expression F, we obtain

F ABCDVABCD - abcdVabcd - low level.

Regardless of the signals on the first 47 and second 48 control inputs of the block, 4 transmission direction selections to the control inputs 15-18 of the switches 3 through the I-HE elements 31-34 are supplied a high level signal. All lines are open until the master transceiver, for example 1.1, chooses a direction, for which, for example, it sends a low level signal to the signal input A to the transmission direction selection block 4 (values of logical variables A a, B b, C c , D d, combi. Ti 7 of the table). In this case, from the output 38 of the first decoder 23, the high-level signal goes through the element OR 27 to the first input of the AND-NOT element 31, the second input of which contains a signal with a high level from the output of the element ORID 35. Then by the coincidence of the high level signals At the inputs of the NANDI element 3I, at its output and further, at the first output of the transmission direction selection unit 4, a low level signal appears, which is fed to the control input 15 of the switches 3.1-3. In the latter, logical elements 7 are opened and the lines (information input 13) go into a closed state. This opens the direction from the master transceiver 1.1 to the executive transceiver 2. At the same time, the outputs 45 and 46 of the transmission direction selection block 4 from the outputs of the element 37 and the element OR 36 receive a low signal and a high signal respectively, which pass to the first and second control the inputs of the analyzer 5 time intervals. The low level signal from the first control input is fed to the input of the counter 51, from the output of which it is fed to the driver 52. From the output of the last signal is fed to the reset input of the memory unit 50, it is set to the zero (initial) state. The high level signal from the second control input is fed to the second (enabling) input of the comparator unit 53, preparing it for receiving the signal from the memory unit 50.

Next, the master transceiver 1.1, selecting the direction, sends a signal to the executive transceiver 2 on a closed line through the circuit: the master transceiver 1.1, the communication channel, the inputs 13 of the 3.1-Z. switchboards, the logic elements 7, the first information outputs 11.1-11. 3.1-З.п, communication channel, executive transceiver 2. Simultaneously from the second information outputs 12.1-12. П switches 3.1-З.п this signal is post 2233778

5 time intervals are transmitted to the signal inputs of the analyzer and then to the inputs from -matter 49 modulo 2. From one of the outputs of the latter (output 5 is selected depending on whether the even or odd number of bits contains the signal of the master transceiver), the signal arriving to the synchronization input of the memory block 50 10 and setting it to a single state. The signal from the output of the memory block 50 is fed to the input of the comparator block 53, and since its BTOpoKf input has an enabling signal 15, (from the second control

input 46) turns it on. By transmitting the signal to executive transceiver 2, the master transceiver 1.1 changes the direction of transmission in the line, for which it removes the low level signal from the line (signal input A) and sets it on the line. (signal input D, values of logical variables A a, B b, 25 C c, D d; combination of 2 tables). Accordingly, at the first output of the transmission direction selection unit 4, connected to the control input 15, a signal selection selection signal 3Q is recorded, and at the control input 18 appears. Thereby, in the switch 3, the logic element 7 is closed, and the logic element 1 O is opened. Simultaneously with the appearance of the signal for selecting the specified direction, a signal from the output of the element 37 appears at the fifth output 45 of the block 4 for selecting the direction of transmission. This signal goes to the first control input 0 45 of the analyzer 5 time intervals and then to the counter input 51. Since, at the output of counter 51, a signal appears for every odd signal at the input, in this case 5 at the input of the driver 52, there is no signal and the output state of memory 50 does not change.

Next, the executive transceiver 2 sends a signal (confirmed) to the master transceiver 1.1 along the following lines: executive transceiver 2, the communication channel, the first information outputs 1I.1 -11.p of switches 3.1-H.p., logic elements 5, inputs 13.1- 13.P switches 3.1-З.п, communication channel, specifying transceiver 1.1. Simultaneously with the second information outputs

five

9

12.1-12. The 3,1-Z.p switches. This signal goes to the signal inputs of the analyzer 5 time and 1 terminals and then to the inputs of the adder 49 n mod 2, from the output of which the signal goes to the synchronization input of the memory block 50, setting it to zero.

In this case, the signal from the output of the memory unit 50 is supplied to the input of the comparison unit 53 with zero potential and turns it off from operation. If the switched channel turns out to be faulty, which corresponds to the absence of a signal at the synchronization input of the memory unit 50, the state of the latter does not change, the comparison unit 53 operates and after a specified time iJ generates a high level signal coming from the second output 47 analyzer 5 time intervals to the first control input of the transmission direction selection unit 4. This signal from the OR-NOT 35 element comes from the low-IMM level to the second inputs of the AND-NOT elements 31-34, as a result of which the first, second, third and fourth outputs 15-18 of the transmission direction selection block 4 appear high the level that goes to the control inputs of switches 3.1-З.п and disconnects the lines including the chosen direction However, until the selection signal set by the previously specifying transceiver 1.1 on the line (signal input D) is removed, the state of the output signal 45 block 4 select the direction of transmission, the state of the account The chip 51, the driver 52 and the memory block 50 do not change. To select a new direction, the master transceiver 1.1 must first remove the signal

of choice. In this case, the signal on the fifth output with

This increases from low to high level, which does not change the state of counter 51 (the counter is controlled by the difference from high level to low);

52 and block 50 of memory. The signal at the sixth output 46 changes from high to low and turns off the unit.

53 comparison, which is set to its original state. As a result, at the second output 47 of the analyzer of 5 time intervals, a low level signal appears, which is fed to the first control

s 0 5 Q

five

0

The main input of the transmission direction selection block 4 and further through the element I.1-AND-NO 35 (unit) to the second inputs of the AND-NOT elements 31-34 removes the blocking of directions.

Then the master transceiver

1.1 realizes re-enable on the board. For this, the selection signal is set again. The analogs of the above-described signal appear at the fifth output 45 of the block 4 for selecting the direction of non-random (difference from high level to low), according to which the state of counter 51 changes (at its output a change in the signal

from a high LEVEL to a low), and the driver 52 generates a pulse arriving at the reset input of the memory unit 50 and setting it to its initial state. At the same time, from the output of the element OR 36, to the second control input 46 of the analyzer 5 time intervals and, further to the second input of the comparator unit 53, a high-resolution signal is received. The switch 3.1-З.п at the same time realizes the chosen exchange direction through the channel. If the initial state is not set when the selection signal is issued (the specifying transceiver 1.1 receives information about the initial state by the level in the wired communication channel and / or by the signal from the first output 54 of the analyzer of 5 time intervals coming through the control line input), it is enough to set the selection signal again. The absence of the initial state, and in this case means a failure, of this direction and the need to choose another direction or diagnosis.

The operation of the master transceiver 1.2 with the executive transceiver 2 occurs in a similar way, only through information inputs 14.1-14.P and through logic elements 9 and 8, controlled by inputs 17 and 16 of the 3.1-Z.p switch.

Mode 2. This mode of operation of the device is carried out to check the communication channel in the area of the switch - master transceiver

1.2 and (or) if one or two of the choice lines A and D fail at once (the low level signal is not removed) of the specifying transceiver 1.1, and

also for listening to the receiver 11

Editor 1.1 exchange between the master I, 2 and the executive 2 transceivers.

The information exchange initiative belongs to the master transceiver 1.1.

Initial state: on the lines of choice A, D and C, B is a high level signal (values of logic variables, B b, C c,).

The driver transceiver 1.1 sets a low level signal on the A and D selection lines (the value of logic variables, D d; a combination of table 8). A high level signal appears at the output 42 of the second decoder of the transmission direction selection block 4, which the first and second elements OR 27 and 28 are fed to the first inputs of the AND-NE elements 31 and 32, since the second inputs of the latter have a resolution (high level signal from the output of the OR-NOT 35 element), the inverted signal (low level signal) passes to exits 15 and 16 of block 4 for example Transmit signals and further to the corresponding control inputs of switches 3 and logic elements 7 and 8. A direction specifies a transceiver 1.1 opens a defining transceiver 1.2 and an executive transceiver 2. Simultaneously from the seventh output 42 of the transmission direction selection block 4, the high level signal arrives at the first input of the analyzer 6 time intervals and then to the second (permissive) input of the block 55 of fright. Also, simultaneously with the fifth output 45, the low level signal is fed to the first control input of the analyzer 5 time intervals and then through the counter 51 and the driver 52 to the reset input of the memory block 50 (sets the initial state of the memory block 50). At the same time, at the second control input 46 of the analyzer 5 time intervals a low level signal prohibiting the operation of block 53

compare, g

: Master transceiver 1.1, opening logic elements 7 and 8 of switches 3, transmits information to master transceiver 1.2 along the circuit: master transceiver 1.1, information outputs 13.1-13.P, communication channel, first information inputs 377 D1 .1 of switches 3, logic elements 7 and 8, the second information (M1 inputs of chunks 3, a spy channel, information pyhoda I 4. -1 A. II, the rear transceiver 1.2. At the same time, this signal goes to the first and second information outputs P. 1-11.G) and 12.1-12.p switches 3, from the first information you course 10 of which it is transmitted to the executive transceiver 2, and from the second to the signal inputs of the analyzer 5 time slots and then to the inputs of the adder 49 mod. 2. At the output 15 of the latter, the signal arrives at the synchronization input of the memory unit 50 and sets it to one the From the output of the memory block 50, the high level signal passes through 20 dton through the first output 54 of the analyzer 5 time intervals to the control input of the analyzer 6 time intervals and to the communication line to the control inputs of the master transceiver 25 transmitters 1.1 and 1.2. From the control input 54 of the analyzer of 6 time intervals, a single signal is fed to the combined input of the .55 and 56 comparison units. But since at the first input 42 of the comparison unit 55 there is a high signal, and the first input 44 of the comparison unit 56 is a low level, the comparison unit 55 starts to perform time monitoring

of the interval in the area of the switch - master transceiver 1.2. The master transceiver 1.2, having received the information from the master transceiver 1.1, must process it in time and set the low level signal on line C. If this condition is met, a signal appears at input 42

from a low level, and if not observed, the time of presence of a high level signal at input 42 (in the presence of a high level signal at input 54) is longer than the specified time T. - t + tjQ, 4TO causes a high level signal at the output of block 55, shutdown of all transmission channels and indicates a malfunction of the switch section - master transceiver

five

1.2.

When setting a low level signal on line C, logical re 13

The variables have the meanings: A a, B B, C c, D d (combination 9 of the table).

The code signal arrives at the fourth decoder 26, at its output 44 a high level signal appears that passes through the third and fourth elements OR 29 and 30 to the first inputs of the AND-NE elements 33 and 34, at the second inputs of which there is a high level signal the output of the element OR NOT 35. The third and fourth outputs 17 and 18 of the block 4 for selecting the direction of transmission and then to the corresponding control inputs of the switches 3 receives a low level signal, which opens the direction specifying the transceiver 1.2 - the specifying transceiver 1.1 and olnitelny transceiver 2.

The opening transceiver 1.2, opening the direction, transmits a confirmation signal to the controlling transceiver along the following circuit: the reference transceiver - sensor 1. 2, information outputs 14.1 14.P, communication channel, second information inputs of switches 3, logic elements 9 and 10, first information inputs of switches 3, communication channel, information outputs 13.1-13.p, setting the transceiver 1.1. Similarly to the described, the same signal goes through the first and second information outputs 11.1-II.p and 12.1-12.p of the switches 3 to the executive transceiver 2 and to the signal inputs of the analyzer 5 time intervals, in which it passes through the adder 49 mod 2 to the input synchronization of the memory unit 50 and sets the latter to the zero state. Therefore, the state of input 54 changes (low level signal), and consequently, the state of control inputs of master transceivers 1.1 and 1.2 also changes, which indicates the normal operation of the section switch - master transceiver 1.2 (provided that the signal at input 42 low level, and at the output of the element OR NOT 35

high level). I

If the test site turns out to be faulty (for example, a channel switch is faulty - specifying transceiver 1.2 and (or) the transceiver did not manage to set the direction for confirmation), then after the time for the block to expire

23377

55 appears a high level signal, which through the OR 57 element enters the output 48 of the analyzer 6 and further to the second control input 5 of the block 4 for the selection of the direction of transmission.

From the control input through the element OR-NOT 35, the low-level signal is fed to the second inputs by the NO-NE 31-34 and blocks their outputs 15-18 and, accordingly, the transmission direction, the transceiver 1.1 does not receive the acknowledgment signal.

In the event of a fault (a low level signal is not removed), one or two selection lines, the master transceiver 1.1, transmits the information exchange initiative with the executive transceiver 2 to the master transceiver 1.2.

At the same time, situations are possible; the low level signal is not removed from selection line A; the low level signal is not removed from selection line D; The signal is removed from the select line A and D.

The first situation means that the master transceiver 1.1 transmits the information to the executive transceiver 2 and must open the reverse direction of transmission, c to the original one. At the control input of the transceiver 1.1 there is a high level signal. However, since the initial direction is not

35 is removed, then the master transceiver 1.1 re-gives information to transceiver 2 (and this informs about the subsequent transfer of control to the transceiver

40 1.2).

When re-transmitting information, the signal at the control input is in-. The giving transceiver changes its value from high to 45 low. Then the master transceiver; 1 exposes a low level signal to the second control input D (values of logic variables, B, 0, D d; table combi 8). At the same time, a low signal appears at control input 46, and a high signal at the second input 42, as a result of which permission to operate unit 53 removes 55 s. The transfer of information to the master transceiver 1.2 from the master transceiver 1.1 occurs as described. Signal on

thirty

15

In this case, the control input 54 changes from a low level (previously set when transmitting from the specifying transceiver 1.1 to the executing transceiver 2) to high, and permission is given to the operation of the block 55. If the section switch 3 — channel — the specifying transceiver 1.2 fails, then after A high level signal appears at the output of block 55, which provides for the disconnection of the transmission (reception) directions.

In normal operation, the master transceiver 1.2, by setting the low level signal to the first ynpate- ling output C, sends a confirmation to the master transceiver.

1.1 (the value of the logical variables,,, D d; a combination of 9 tables).

In this case, a low signal appears at the second input 42, and a high level signal appears at the second input 44. When transmitting an acknowledgment (at the moment when the switch passes the switch 3) the signal at the control input of the transceivers 1. 1 and 1.2 changes from high to low, after which transceiver 1.2 opens the direction executive transceiver 2 is the master transceiver 1.2 and the master transceiver 1.1. The opening of the specified direction is as follows. Master transceiver

1.2 The signal from the low level to the high level on the control input removes the low level signal from the first control output C (the values of the logic variables A a,

B, c, d (i; combination of table 8) and then exposes a low level signal to the control output B (values of logical variables,, combination of table 10).

I.

When a low level signal is removed from control output C at input 44, a low level signal appears, and when a low level signal is set, output B at input 46 is a high level signal. At the same time, the logic elements 8 and 10 of the switches 3 through the circuit open: the signal inputs A, B, D (low level) of the transmission direction selection unit 4, the third decoder

2337716

25 (high level at output 43), elements OR 28 and 30, elements AND-NOT 32 and 34, second and fourth outputs 16 and 18 of the block 4 for selecting the direction of transmission 5, corresponding control inputs of switches 3, control inputs of logic elements 8 and 10. After the direction is opened, the executive 10 transceiver 2 sends acknowledgment information to the communication channel. Further, the process of transmitting is carried out as described above (description of mode 1).

15 The second situation means that the master transceiver 1.1 transmitted information to the executive transceiver 2 and has already received confirmation from it. In this case, the primary transceiver 1.1 transfers the initiative to the master transceiver 1.2 in the same way as described, except for re-informing the executive transceiver 25 to 2 before choosing the direction

exchange with the master transceiver 1.2.

In the first and second situations considered, executive transceiver 0 transmitter 2 controls the exchange and transfer of control between master transceivers 1.1 and 1.2. This control precedes the sending of confirmation information to the communication channel.

In the third situation, a transceiver is performed between the master transceiver 1.2 and the executive transceiver 2. In this case, the master transceiver 1.1 listens to all the transceiver information.

five

0

Mode 3. This mode of operation of the device is implemented to check the communication channel in the area of the switch - master transceiver 1.1. and (or) in the event of a malfunction (low level is not removed) of one or two of the choice lines C or B of the specifying transceiver 1.2 as well as for listening to information about the exchange between the specifying transceiver 1.1 and the executive transceiver 2.

The operation of the device in mode 3 is performed similarly to the operation of the device in mode 2. At the same time, to transfer the initiative to the master transceiver

The heading 1.1 uses the fourth dispatching unit 26 of the transmission direction selector Blur 4 (the values of the logic variables, B - b, C c, D - d; table combination .5), to receive a confirmation signal from the specifying transceiver 1.1, the second decoder 24 (values of logical variables A a,, C c, D d, combination 11 of the table), and to receive a confirmation signal from executive transceiver 2 - the third decoder 25 (values of logical variables, B b, C c, D d combination 6 of the table ).

Claims (2)

Invention Formula 1. The device for controlling prompt communication channels by aut. St. No. 1135012, characterized in that, in order to increase the depth of control and increase the reliability of the device, a second time interval analyzer is inserted in it, which is connected to the second control input of the transmission direction selector, the sixth output of which is connected to the second input of the comparison unit the first time interval analyzer, and the seventh and eighth outputs are connected respectively to the first and second inputs of the second time interval analyzer, the control input of which is connected to the first output of the first analysis the time interval jams, the transmission direction selection block is implemented in the form of first, second, third and fourth NOT elements, whose inputs are the signal inputs of the transmission direction block, the first, second, third and fourth decoders, the signal inputs of each of which are connected respectively to the inputs and the outputs of the corresponding elements NOT, the first element OR, the first input of which is connected to the first output of the first decoder, and the second input is connected to the output of the second decoder, the second element OR, ervsh input coupled to the second output of the first decoder, the second input - with the output of the second depshfratora, and the third input - with the output of a third decoder, a third OR gate, a first input 2; P771 which is connected to the third output of the first decoder, and the second input is connected to the output of the fourth decoder, the fourth element OR, 5 whose first input is connected to the fourth output of the first decoder, the second input to the output of the third decoder, and the third input to the output of the fourth decoder, the first, second, third and fourth elements AND-NOT, the first input of which is connected to the output of the corresponding element OR element OR NOT. the output of which is connected to the second The 15 inputs of the NAND elements, and the first and second inputs are respectively the first and second control inputs of the transmission direction selection block, the fifth IL element, the first, second, third and fourth the inputs of which are connected respectively to the first, second, third and fourth outputs of the first decoder, and the fifth input is connected to the output of the third decoder, and element And whose inputs are connected to the inputs of the corresponding elements NOT, while the outputs of the first, second, third, and fourth elements The NAND and the element AND, the output of the fifth element OR and the outputs of the second and fourth decoders are respectively the first, second, third, fourth, fifth, sixth, seventh and eighth outputs of the transmission direction selection unit. 2. The device according to claim 1, of which is that the second time interval analyzer contains an OR element, the first and second time interval comparison blocks, while the outputs of the first and second time comparison blocks The inputs are connected respectively to the first and second inputs of the OR element, the output of which is the output of the second time interval analyzer, the first inputs of the first and second time comparison units are combined and are controlled by the second input of the second time interval analyzer, volts swarm input of the first comparator unit time slots and a second input of the second block comparing the time intervals are respectively first and second inputs of the second analyzer timeslots. thirty 35 40 45 50 55