SU1223361A1 - Ring counter - Google Patents

Abstract

This invention relates to automation and computing. It can be used in control and regulation systems, data processing and automatic control as a counter, distributor, frequency divider in the low and infra-low frequency ranges. The purpose of the invention, the increase in reliability, is achieved by reducing the number of controllable contact groups of the bit relays. The counter contains discharge relays 1-10, blocking resistors 11-20, counting buses 21 and 22, storage capacitors 23 and 24, frequency divider 25 into two with switching groups 25.1 and 25.2, counter resetting node 26, relay 27 a reverse with the number of switching groups 27.1-27.10, equal in number to g-l of the bit relays 1-10, the input relay 28 and the power supply buses 29 and 30. 1 il. (L 25-f 21 PeSeflc 8khod Yu 1C SO 00 o

Description

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The invention relates to automation and computing and can be used in control and regulation systems, data processing and automatic control as a counter, distributor, frequency divider in the range of low and infra-low frequencies.

The purpose of the invention is to increase reliability by reducing the number of control contact groups of the discharge relays.

The drawing shows a schematic diagram of a ring counter, which includes discharge relays 1-10, blocking resistors 11-20, the first counting bus 21 and the second counting bus 22, storage capacitors 23 and 24, the frequency divider 25 by two with the first and second switching circuits 25.1 and 25.2, node 26 for resetting the counter, relay 27 of the reverse with the number of switching groups 27.1-27.10, equal to the number of discharge relays 1-10, input relay 28 with switching group 28.1, the first second tires are 29 and 30 feed.

In accordance with the drawing, in a ring counter, containing an input relay 28, a reverse relay 27, a frequency divider 25 into two, a resetting unit 26, discharge relays 1-10, blocking resistors 11-20, storage capacitors 23 and 24 , the first terminals of the windings of the odd bit relays 1,3, ..., 9 are connected to the first counting bus 21, which through the closing and switching contacts of the second switching group 25.2 of the divider 25 of the input pulse frequency by two is connected to the first power bus 29 and through the first the capacitor capacitor 23 - to the second power bus 30, the first terminals of the windings of even-numbered relays 2.4, .. 10 are connected to the second counting bus 22, which is connected to the adjacent contact of the second group 25.2 of the frequency divider 25 into two and through the second storage capacitor 24 to the second bus 30 units, a frequency divider 25 into two, and a reset unit 26 are connected between the first and second buses 29 and 30 of the terminal.

1.10 through blocking resistors 11,12, .. ... 20 - to the second power bus 20, each switch uses a junction group 27.1, 27.2, ..., 27.10 of the reverse relay contact 27, the second winding pins of all the discharge relays 1 , 2, ..., 10 are connected respectively to the closing contacts of the switching groups 27.2, 27 .3, ..., 27.1 relays 27 reverse the subsequent bits and to the breaker 1m contacts of the switching groups 27.10, 27.1, ..., 27.9 relays 27 reverse the previous bits, and the switching contacts of switching groups 27.1, 27.2, ..., 27.10 relays 27 reverse through the closing and switching contacts of groups 1.1, 2 .1, ..., 10.1 bit relays 1,2, ... 10 of their bits are connected to the second power supply bus 30.

The ring counter operates as follows.

When the power is turned on, the node 26 for setting the counter to the initial state generates a short pulse with amplitude E (E is the power supply voltage), under which the discharge relay 1 operates and is blocked through the resistor 11, the discharge relays 3,5,7 and 9 do not work.

thirty

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40

45

50

since the current Ip through the windings of the discharge relays 1-10 in the initial state, the selection of the values of the resistors 11-20 is such that the inequality is fulfilled:

RTP p cf),

where is the discharge discharge current igj

relay i

Ip is the current through the coil of the discharge relay in the initial state and the trigger current of the discharge

relay.

The contacts of group 1.1 of relay 1, closing, through the disconnecting and switching contacts of group 27.1 of relay 27 of the reverse shunt the blocking resistor 12 of relay 2, preparing for the operation of relay 2. The counter is reset.

When the first impulse arrives at the input relay 28, the latter is triggered and its contacts of group 28.1 trigger the relay, the output of the installation unit 26 to the frequency source 55, the contacts of the group state are connected to the second 25.1 of which the coil of the discharge relay 1, bus 21 and connect the bus 22

second pins of the bit coil windings

since the current Ip through the windings of the discharge relays 1-10 in the initial state, the selection of the values of the resistors 11-20 is such that the inequality is fulfilled:

RTP p cf),

where is the discharge discharge current igj

relay i

Ip is the current through the coil of the discharge relay in the initial state and the trigger current of the discharge

relay.

The contacts of group 1.1 of relay 1, closing, through the disconnecting and switching contacts of group 27.1 of relay 27 of the reverse shunt the blocking resistor 12 of relay 2, preparing for the operation of relay 2. The counter is reset.

When the first pulse arrives at the input relay 28, the latter is triggered, and its contacts of group 28.1 trigger the relay to the power bus 29, as a result of the relay

2 is triggered because the contacts of group 1.1 of relay 1 remain closed. For some time ij after disconnecting bus 21 from power supply bus 29, the amount of delay t is determined by the value of capacitor 23 and should be sufficient to reliably trigger any relay 1-10. After the capacitor 23 of the capacitor 23 is fully discharged, the contacts of the C1 and C1 contacts open, but the relay 2 remains switched on via the blocking resistor 12. The closed contacts of the group 2.1 of the relay 2 bypass the resistor 13 of the relay 3, preparing for the operation of the relay 3.

When the second pulse arrives at the input relay 28, the latter is triggered and by its contacts of group 28.1 connects a split capacitor 25 to the winding of relay splitter, relay divider 25 turns off, and contacts of group 25.2 switch, disconnect bus 22 and connect bus 21 to power bus 29.

As a result, the relay 3 trips, since the contact of group 2.1 of relay 2 remains closed for some time t, after disconnecting the bus 22 from the power supply bus 29, the delay tj is determined by the value of the capacitor 24 and must be sufficient to reliably trigger any relay 1-10.

After the capacitor 24 of the capacitor 24 is completely discharged, the contacts of group 2.1 open, but the relay 3 remains turned on through the blocking resistor 13. The closed contacts of group 3.1 of the relay 3 bypass the resistor 14 of relay 4, preparing for the operation of the relay 4.

Thus, with the arrival of the after-cycle of the input pulses, alternating relays 4–10 alternate between, then discharge relays 1–3, etc., i.e. the counter drives one on the ring in direct count mode.

To transfer the counter to the counting mode, it is necessary to apply power to the winding of the reverse relay 27. If at the moment of transfer of the counter to the countdown mode the bus 21 is connected to the power supply and relay 5 is activated, then the closed contacts of the relay 5.1 relay 5 through the closing and switching contacts of the group 27.5 of the reverse relay 27 bypass the resistor

14 relays 4 preparing to operate the relay 4.

When the next input pulse arrives, bus 21 is turned off, and bus

22 is connected to the power bus 29 and the relay 4 is activated; its contacts of group 4.1, short-circuit, are shunted through the short and the switching contacts of group 27.4 of the reverse relay 27

resistor 13 relay 3, preparing for the operation of the relay 3.

Thus, as they arrive, the pulses alternate relays 3,2 and 1, then 10, 9 and 8

etc., i.e. the counter drives one in a ring in the countdown mode.

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Claims (1)

Invention Formula An annular counter containing an input relay, a reverse relay, a frequency divider by two, a reset unit, a discharge relay, blocking resistors, storage capacitors, the first terminals of the windings of odd-bit relay relays are connected to the first counting bus, which through the disconnecting and switching The contacts of the first group of the frequency divider are connected to two to the first power bus and through the first storage capacitor to the second power bus, the first terminals of the even-digit discharge windings the relays are connected to the second counting bus, which is connected to the closing contact of the first group of the frequency divider by two and through the second storage capacitor to the second power bus, the frequency divider by two and the reset unit are connected between the first and second power buses, the node output initialization is connected to the second The winding of the first bit relay, characterized by the fact that, in order to increase reliability by reducing the number of control groups of the contacts of the discharge relays, the second terminals of the bit windings of the relay switch through the blocking resistors to the second power bus. the contact group of the reverse relay, the second winding pins of all bit relays are connected respectively to the closing contacts of the switching groups of the reverse relay after 51223361 the rest of the bits and to the disconnecting groups of the reverse relay through the relay contacts of the switching groups of the relay and the switching contacts of the groups of the discharge of the previous discharges, and the forward relays of their bits connect the switching contacts of the second power bus.