SU1206811A1 - Device for processing experimental data - Google Patents

Abstract

The device relates to computing and can be used in medicine. The aim of the invention is to increase the performance of the device and the reliability of the results by automatically analyzing the test signal during the course of the experiment. The device contains three comparison schemes, three rectangular pulse generators, AND elements, one-shot, OR elements, reversible counter, duration counter, interval counter, address counter, pulse counter, register, three memory blocks, delay elements, comparison circuit, switch, digital-to-analog converters, tape drive, control unit. 3 il. with S (L with you about O) 00

Description

one

The invention relates to computing and medical engineering and can be used to automate experimental, for example, neurophysiological studies,

The aim of the invention is the device performance and the accuracy of the results by automatically analyzing the test signal in the process of conducting an expert.

FIG. 1 is a diagram of the device j in FIG. 2 is a diagram of a control unit; in fig. 3 is a diagram of counter a, cres.

The device contains circuits 1 - 3 comparisons S generators 4-6 rectangular pulses, elements AND 7 - one-shot 17, elements OR 18-21 reversible counter 22, counter 23 duration S counter 24 interval values, counter 25 addresses, counter 26 pulses, register 27 , blocks 28-30 of memory, delay elements 31-35, comparison circuit 36, switch 37, digital-to-analog converters (D / A converters) 38 and 39, accumulator

40 On a magnetic tape, control unit 41, triggers 42 and 43, element AND 44., reversible counter 45, element 2И-ШШ-НЕ 46, comparison circuit 47, counter 48, reference voltage reference node 49, indicator 50, node 5 switches for transferring signals 52-65.

The device works as follows.

The switches of the node 51 in the control block 41 are set to the Analysis, Output to Oscilloscope, Intervals. The signal 53 from the output of the block 41 is fed to the inputs of the elements And 7 - 10 allowing them to work. Signal 54 Output to oscilloscope from block output

41 arrives at the element 14 And, allowing the passage through it of the generator pulses 5. Signal 59 Intervals

 the output of the control unit 4 is received at the input of the switch 37, ensuring the passage of information from the terminal. the outputs of the memory block 30 through the ator 37 to the input of the D / A converter 39 and the online input of the storage device 40. Interval switch ъ the switch is on

068.1 2

Amplitude or switchability. At the same time, the corresponding signal 57 or 58 from the output of block 41 is fed to the input of switch 37, ensuring the passage of signals from the outputs of block 28 (amplitude) or block 29 (duration) of memory through the switch to the inputs of the DAC 39 and information input of the accumulator 40.

0 By pressing the Reset key at node 51, signal 52 Reset from the output of block 41 resets counters 25, 26 and, through the OR elements 18 and 19, resets register 27 and counters 23 and 24.

15 The analog signal under study and the output signal from the D / A converter 38 are fed to the inputs of comparison circuits 1 and 2. These signals are compared with each other. If the input voltage is higher than the voltage 20 from the output of the NDL 38, the circuit 1 supplies the input element And 7 potential allowing the impulses of the generator 4 to pass through the element 3 to the summed down input of the reversible counter 22. If the input voltage is less than at the output of the D / A converter 38, then the circuit 2 applies a potential to the input of the element 8, which permits the passage of the pulses of the generator 4 through

0 element 8 to the subtracting input of the reversible counter 22. The signals from the output of the counter 22 are fed to the input of the DAC 38 and accordingly change the voltage at the output of the DAC 38. Thus, the reversible counter 22 together with the DAC 38, comparison circuits 1 and 2 and elements And 7 and 8 is the next A / D converter. The signals from the output of the reversible counter 22, representing the code of the current amplitude of the input voltage, also go to the information input of the register 27 and the inputs of the comparison circuit 36.

The input voltage of the comparison circuit 3 is received, and a signal 60 is received from block 41 — a threshold voltage that determines the level of amplitude discrimination and is adjustable at the reference voltage source in block 41. If the analyzed voltage exceeds the threshold voltage (i.e., the useful signal), then the circuit 3 outputs the inputs 5 of the elements 9 and 10 of the potential which permits the passage of the pulses of the generator 4 through the element 9 to the i the counting input of the counter 23 long5

0

0

and prohibits the passage of the impulses of the geerator 4 through element 10 to the counting input of the counter 24 interval. If the analyzed voltage is less than or equal to the threshold, i.e. the input signal is less than or equal to the noise level (amplitude discrimination level), then the potential from the output of circuit 3 prohibits the passage of generator 4 pulses through element 9 to the counting input of counter 23 and allows the passage of generator 4 pulses through element 10 to counting input of counter 24. Thus, in the counter 23, a number is accumulated that is a multiple of the time duration of the signal that exceeds the threshold level, i.e. the duration of the recorded pulse. The counter 24 accumulates a number that is a multiple of the signal duration less than or equal to the threshold level, i.e. the value of the interpulse interval.

The signal from the output of the AND element 9 through the delay element 31 is fed to the enabling input for recording the amplitude in the register 27. Thus, in the register 20 there is a maximum amplitude value, i.e. peak amplitude of the recorded pulse.

The signals from the outputs of register 27, counter 23 and counter 24, respectively, arrive at the information inputs of memory blocks 28-30, where the most important characteristics of each recorded pulse are memorized (amplitude in block 28, duration in block 29, inter-pulse interval in block 30) .

The storage of the impulse response characteristics in the memory blocks 28-30 and the cleaning of the reversible counter 22 and the counters 23 and 24 are performed as follows. The signal from the output element And 10 is fed to the input element And II. The other input element AND 1 1 receives the potential from the output of non-zero counter 23. The signal from the output of element 11 is generated at the moment when the pulse registration is completed and the interval value starts (the pulse from the output of element 10) is fed to the input of element OR 20 , through the entry delay entry element 32 of the recording unit 28, the memory unit 29, recording the amplitude and duration of the queue 068114

pulse, and the counting input of the counter 26 pulses. The same signal from the output of the element And 11 through two elements 32 and 33 of the delay and through the element OR 18 arrives at the installation inputs of the register 27 and the counter 23.

The signal from the output element And 9 enters the input element And 12, on

10 another input which receives the potential from the output of the counter 24. The signal from the output of the element And 12, is formed, at the moment when the count of the value of the interpulse interval ends

15 and the registration of the next pulse begins (pulse from the output of the element AND 10), enters the input of the element OR 20, through the element 34 of the delay arrives at the input of the recording resolution

20 block 30 of memory, recording the value of the next interpulse interval. The same signal from the output element And 12 through the elements 34 and 35 of the delay and through the element OR 19 enters

25 to the installation input of the counter 24.

The recording of the next impulse response (amplitude, duration, and interval) into the corresponding memory block occurs only

3Q once, because after writing to the memory, the counter 23 or counter 24 is set and the signal of a non-zero state of the corresponding counter disappears.

The signal from the output of the element OR 20, generated both when recording the amplitude and duration of the next recorded pulse, and when recording the values of the next interpulse interval in the memory, arrives at the enabling input of the address counter 25 and overwrites the information from the counter 26 output in the address counter 25. The signals from the output of the address 25 address are fed to the address inputs of memory blocks 28–30, ensuring the recording of the characteristics of the next pulse into the corresponding memory block at the next address equal to the serial number

35

40

50

registered pulse.

In addition, the signals 62 from the output of the counter 26 arrive at the input of the indicator 50 of the control unit 41, providing an indication of the number of registered pulses. If the numbers of recorded pulses increase too slowly, then

the threshold voltage is too high and the experimenter can reduce it with a potentiometer. If the number of registered pulses approaches the limit, limited by the capacity of blocks 28–30, then the experimenter can turn off the Analysis switch at node 51 of the mode switches, interrupting the filling of memory 8 and turn on the Output to the plotter, Output to the drive or leave the Output to oscilloscope mode. In the Output to oscilloscope mode (and this mode is usually set simultaneously with the setting of Analysis mode), the signal 54 Output to the oscilloscope from the output of control station block 41; it drops to element 14, allowing the generator 5 to pass to input element 6. And to another input element I 16 receives a signal from the output of the one-shot 17, to the input of which from the output of the element OR 20 a pulse arrives either at the end of the registration of the next pulse (before recording the amplitude and duration of the registered pulse in blocks 28 and 29 (this pulse And 12), or when the determination of the next interval is completed (before recording the interval value in memory block 30; this pulse is generated by AND 11) The signal from the one-vibrator output blocks the passage of generator 5 pulses through AND 16 to the counting input of the address counter 25 on a time sufficient for storing in the counter 25 the address of the number of the next recorded pulse and the duration or interval value in blocks 28 and 29 or in memory block 30. In the absence of a signal from the output of the one-shot 17 through the AND 16 element to the counting input of the address counter 15, pulses are transmitted from the output of the 1SH 21 element. In the address counter 25, the address search with the generator frequency 5 is organized (in the mode: Output to the plotter is the frequency b In the Output to Drive mode, this is the pulse repetition frequency of the playback track, determined by the recording density of the tape recorded on the tape beforehand.

magnetic tape using a computer). The enumeration of addresses in the counter 25 is organized according to the ring principle. When the r code in the counter 25 becomes equal to the code from the output of the counter 26 to the information input of the counter 25, the next pulse arriving at the counting input of the counter 25 sets the fC to zero, i.e. a zero memory address is selected. Subsequent pulses arriving at the counting input of the address counter 25 add one to its content- 5 MU, i.e. increase the current address by one until the contents of the counter 25 are again compared with the contents of the counter 26 of the number of recorded pulses. In this way, a cyclic review of an already filled memory section with a generator frequency of 5 is provided.

On the oscilloscope screen, a stable (repeated cycling with a high frequency) image of a graph of changes in amplitude, duration, or pulse intervals from the beginning of the experiment to the moment of observation is formed. The graph contains as many points

0 how many pulses are registered. When registering the next pulse, the graph is supplemented with one more point. Observing these graphs, the experimenter judges the course of the experiment, can correct it, since it immediately sees the final result. The signals from the outputs of blocks 28 to 30 of the memory are received at the information inputs of the switch 37. The signals are 57 Amplitude,

0 58 Duration, 59 Interval, coming from the outputs of block 4I to the enabling inputs of the switch 37, allow the passage of signals from the outputs of one of the blocks 28–30 packs through the switch 37 to the input 11DP 39 and information input of the accumulator 40. Output signal of the D / A converter 39 device output and in oscillator mode, the oscilloscope is connected

g to oscilloscope. Thanks to the organization of the cyclic viewing of memory blocks, the oscilloscope displays a graphical image of the analysis results: a graph of the recorded

, 5 amplitudes, durations or intervals depending on the selected mode. Outputting oscilloscope results of the studied impulses.

interrupts for a very short time (this time is determined by one oscillator 17, which blocks element 16) at the moment of recording in the memory blocks the values of the amplitude and duration of the next registered pulse or the value of the next registered interval. This suspension is almost imperceptible to the experimenter and practically does not prevent him from constantly observing the results of the analysis in a convenient graphical form on the screen of the oscilloscope. B mode Output to the plotter The speed of the points through the DAC 39 to the plotter connected to the output of the DAC 39 is determined by the frequency of the generator 6. The Output to the plotter mode is turned on by the experimenter after completing the analysis and turning off the Analysis switch. After one of the graphs, for example, the amplitude graph on the plotter, is outputted, the experimenter turns off the Output Mode on the plotter, sends a reset signal 52 and sets the address counter 25 to zero at 52 and switches to the duration plotting mode, first Switch Duration, and then switch Output to the plotter in node 51 of the switches. Thus, at the end of the output of the graph of durations, you can produce a graph of the integrals.

In the Output to the accumulator mode, the recording rate for information from one of the memory blocks 28–30 is determined by the frequency of arrival of the tracking pulses from the output of the accumulator 4 Before the first activation of the output mode to the accumulator, the experimenter rewinds the magnetic tape to the marker. There is information on the magnetic tape previously recorded in a standard way with the help of computer blocks whose size is equal to the size of one memory block. The blocks are separated by interblock intervals. When starting a computer, usually one or several tracks inside the magnetic tape zone are filled with units. During the experiment in track mode with motion and tape back

it is read, an impuh is formed - with p.5 pro x; er: reproduction, which from the output, accumulator 40 enters n. g: entrance accompaniment zash-si

storage device --O, providing a recording to the same magnetic tape fed through the switch 37 to the information input of the storage 40 dnnK of one CU of blocks 28 - 30 of memory. Before turning on the signal 65, the experimenter turns on the signal 52 and sets the address counter 25 to zero. When switching output mode to. The control unit 41 generates a signal 63 Motion, which is maintained until the tape moves back to the full information zone and disappears, providing a stop when the tape turns out to be approximately in the middle of the next interband gap. By pressing the Reset key, the signal enters the inputs of the flip-flops 42, 43 and sets them. Pressing the Output BHO button on the magnetic tape: -1 flip-flops 42 and 43 briefly (non-latching key) low potential is applied, reset; - either the flip-flops are in one state. The output of the flip-flop 42 of block 41 shows the signal 63 Movement to enable tape. When moving, the unit for reading and writing the magnetic tape while the carrier is moving backwards ensures that the control is read and the new information is recorded. The tracking signals appearing at the output of the accumulator 40 are fed to the synchronizing input of the trigger 43, again resetting the trigger 43, and to the installation input of the reversible counter 45. The signal from the output of the trigger 42 and the signal from the inverse output of the trigger 43 is fed to the inputs of the And 44 element , permitting the passage of pulses 61 of the generator through element I 44 to the summing input of the reversible counter 45. Thus, as the magnetic tape moves inside the information zone, the inputs of the reversible counter 45 simultaneously receive impulses of tracking and the setup input and the generator 6 signals to the summing input. Since the frequency of arrival of tracking pulses is much higher than the frequency of the oscillator signals, the content of the reversing counter is 45

will be zero. At the end of the information zone, the pulses stop flowing. Generator 6 signals continue to flow to the summing input of the reversible counter 45, increasing its content. When it increases to 1 5J, the next impulse 61 of generator 6 will cause an overflow signal, which from the spin code 45 enters the synchronous trigger input 42 and is reset, terminating the signal of the 63 Moving shaft and thus stopping the KarHH rHjr o tape outside the information zone.

A drive 40 with a reverse reading and writing support unit: l-; the carrier is a standard drive on an IZOT 5003 magnetic tape, in which a switch is additionally installed, which allows you to erase the circuit during write; on

inputs

 setting record state

(HSS) and the state of reproduction (SPM) is applied to the resolving potential (ground) and the input direction of the movement (NPR) is given a high potential S that determines the output of the compressed direction of movement.

Introduced additions ensured- :() t 7zoem () the ability of simultaneously reading and recording magnetic tape during reverse movement of the carrier, Impulse. arriving at the counting input from; the reticulator 48 (Fig. 3) arrive in the same way / heh input element 46. At the inputs - 1 comparison post-fall signals i :. you-; counter 26 (the input of the counter 26) and the output of the counter 48. When the contents of both counters 49 and 26 are equal, the output from the comparison circuit 47 is fed to the element 46, the next counting impulse through the installation counter: start of counter 48; in the way, when the counter reaches 25 code, equal to the code in counter 26, m., e: the number of registered pulses; the counter 25 is reset / l billing the addresses again starts from zero; The reset of the counter 25 is performed by the driver Nal 52 from the control unit 41;

Formula invented

Device for processing experimental data s containing nakoy

0

a tape-recorder unit, a unit ----; iaBjiei-U; Fi, register 5 is the first element, the switch is a circuit of a circuit of 5 counts of pulses, which is: - a. y p, weight te ;, that O; from the hunt for the prog program and for the accuracy of the results by means of automatic a ;; aliza of the test son 3 of the process of conducting the experiment in a bliss, the second, third and fourth diagrams were introduced: compare the generator to the right box; x and the tool - СО53 5 elements And one-shot, from the second to the fourth element: - ,; OR, regenzggensh account - IR 5 counter / duration, counter inter session S address counter, three memory blocks, delay elements .; two 1, if the analogue transforms are Vate.n e vyho.d the first of which. is the device, the first inputs of the first, 1, and 3 third circuits are connected to the input of the device, the output of the second digital-to-analog converter is connected to the second inputs of the first and second comparison circuits; the output of which are connected respectively HeTC.TFie.HHo to the first inputs of the first t- :; g; Elements I. The second input of the third comparison circuit is connected: the output of the threshold eg: -; In the case of a control unit, the output of the third comparison circuit is compared with the first one. the input of the third zlemeite And and with the inverse input of the fourth zlemei.ta I. the second ;; xoiibi elements I, from the first to the third, and the direct input of the city | .fourth: the electer And connected to the output of the first Tioro generator, rectangular - aul., third inputs of elements I, C; the first to the third, connected to ghoa; the signal of the signal is ana ... by the control block; the outputs of the first and second j.ffti-.veHTOB AND are connected respectively- - 1C - summed and subtracted inputs; 1 reversible counter; output: the output is connected to the information; the register goes, to the input of the second in-ifhpoaKa.noroBoro converter and to the n: Main input of the fourth comparison circuit, allowing the inputs of the register, the inputs, respectively, to the outputs of the first delay element and the fourth comparator circuits, the output of the register is connected to the second input — the pin of the first comparison circuit and the information (.; ai: - 1tom7u input of the first memory block., —.the output of the third element AND connect to the first input of the the counting input of the duration counter and to the input of the first element of the delay The information output of the duration counter is connected to the information input of the second memory block, the output of the non-zero state signal of the duration counter is connected to the first input of the sixth element I, the output of the fourth element I is connected to the counting input of the interval counter and the second input of the sixth element And, the output of which is connected to the first input of the first OR element and to the input of the second delay element, the output of which is connected to the input of the third delay element, with the recording enable inputs of the first and second memory blocks With the counting input of the pulse counter, the information output of the interval counter is connected to the information input of the third memory block, and the inverse output of the zero state of the counter is connected to the second input of the fifth AND element, the output of which is connected to the second input of the first OR element and the input of the fourth delay element, the output of which is connected to the input of the fifth delay element and to the recording enable input of the third memory block, the outputs of the third and fifth delay elements are connected respectively to the first inputs in the third and OR elements, the output of the second element OR is connected to the setup inputs of the register and the duration counter, the output of the third element R1PI is connected to the installation input of the interval counter, the output of the first element OR is connected to the enable input of the address counter and the one-shot output, the seventh , the eighth and ninth elements And are connected respectively to the inputs of the fourth element OR, the output of which is connected to the first input of the tenth element And, whose output is connected to the counting input of the address counter The output of which is connected to the address inputs of the first, second and third memory blocks, the outputs of which are connected respectively to the information inputs of the switch, the enabling inputs of which are connected respectively to the first,

the second and third switching outputs of the control unit, the switch output is connected to the input of the first digital-to-analog converter and to the information input of the tape drive, the output connected to the tracking pulse inputs of the control unit and tape drive and the first input of the seventh element, And the second output the generator of rectangular pulses is connected to the first input of the eighth element And, the output of the third generator of rectangular pulses is connected to the first input of the ninth element And with The second input of the control unit, the second inputs of the seventh, eighth and ninth elements And are connected respectively to the first second and third outputs of the output resolution of the control unit, the output setting of the initial state of which is connected to the second inputs of the second and third elements OR, to the installation inputs of the address counter and pulse counter, the output of the one-shot is connected to the second input of the tenth element And, the output of the pulse counter is connected to the information input of the address counter and the signal input of the control unit, the output signal The control unit is connected to the motion control input of a tape drive, the control unit contains two triggers, AND, a reversible counter, an indicator, a reference voltage setting unit, and a mode switch node whose outputs, from first to eighth, are respectively the setup outputs of the initial state of the analysis signal, the first, second, and third inputs of the output resolution by the first, second, and third commutation outputs of the control unit; the setup output of the mode switch node connected to the single inputs of the first and second triggers, the zero inputs of which are connected to the first output of the mode switch node, the synchronization input of the first trigger connected to the overflow output of the reversible counter, the installation input of which and the synchronization input of the second trigger are connected to the tracking input of the control unit, summing the reversing input the counter is connected to the output of the element And, the output of the first trigger is connected to the first input of the element And and to the output of the motion signal of the control unit , the second and third inputs of the element And are connected respectively with inverse

the output of the second trigger and the clock input of the control unit, the indicator input is the signal input of the control unit, the output of the threshold voltage setting node is the output of the threshold voltage of the control unit.

rm Sr- C VO J r IT «r tr IT, Ur O

Csj

6s

at

Order 8715/51 673Subscription

BHHIillrf USSR State Committee

on the matters of inventions and discoveries 113035 ,, Moscow Zh-35, Raua Ska nab., d, A / 5

Filial PPP Patent g, Uzhgorod, st. Project, 4

hj 1 ".-, .-. T / I - -, .... „

qS b fmg. 3

Claims (1)

Formula invented and i'm 55 A device for processing experimental data containing a magnetic tape drive, a control unit, a register, the first is an OR element. a switch, a first comparison circuit, a pulse counter, etc., and so on, with that, p. In order to increase the productivity and reliability of the results by automatically analyzing the test signal during the experiment, the second, third and fourth comparison schemes, three rectangular pulse generators, AND elements, a single-shot oscillator, and a fourth OR element, a reversible counter, and a duration counter are introduced into it. , interval counter, address counter, three memory blocks, delay elements, two digital-to-analog converters, the output of the first of which is the output of the device, the first inputs of the first, second swarm and the third comparison circuits are connected to the input of the device, the output of the second digital-to-analog converter is connected to the second inputs of the first and second comparison circuits; the outputs of which are connected respectively to the first inputs of the first, second elements AND, the second input of the third comparison circuit is connected to the output of the threshold voltage of the control unit, the output of the third comparison circuit is connected to the first input of the third element And and the inverse input of the fourth element And, the second inputs of elements And ,, from the first to the third, and the direct input of the fourth AND element is connected to the output of the first rectangular pulse generator, the third inputs of the And elements, from the first to third, are connected to the output of the analysis signal of the control unit avleniya; the outputs of the first and second Y'ymentosis And are connected respectively by the summing and subtracting inputs of the reversible counter, the output of which is connected to the information input of the register, to the input of the second digital-to-analog converter and to the first input of the fourth comparison circuit, the enable inputs of the register are connected respectively to. the outputs of the first delay element and the fourth comparison circuit, the output of the register is connected to the second input of the fourth comparison circuit and the information input of the first memory block, the output of the third element And under 120681] keys to the first input of the fifth element And, to the counting input of the duration counter and to the input of the first delay element , the information output of the duration counter is connected to the information input of the second memory block, the output of the signal of a nonzero state of the duration counter is connected to the first input of the sixth AND element, the output is of the fourth AND element is connected to the counting input of the interval counter and to the second input of the sixth AND element, the output of which is connected to the first input of the first OR element and to the input of the second delay element, the output of which is connected to the input of the third delay element, with recording permission inputs of the first and second blocks memory and with a counting input of the pulse counter, the information output of the interval counter is connected to the information input of the third memory block, and the inverse output of the sign of zero status of the counter is connected to the second input the fifth AND element, the output of which is connected to the second input of the first OR element and the input of the fourth delay element, the output of which is connected to the input of the fifth delay element and to the write enable input of the third memory unit, the outputs of the third and fifth delay elements are connected respectively to the first inputs of the second and the third OR element, the output of the second OR element is connected to the installation inputs of the register and the duration counter, the output of the third OR element is connected to the installation input of the interval counter, the output of the first of the OR element is connected to the enabling input of the address counter and with the output of the one-shot, the outputs of the seventh, eighth and ninth AND elements are connected respectively to the inputs of the fourth OR element, whose output is connected to the first input of the tenth AND element, the output of which is connected to the counting input of the address counter, the output of which connected to the address inputs of the first, second and third memory blocks, the outputs of which are connected respectively to the information inputs of the switch, the permitting inputs of which are <-connected respectively from the first m, the second and third switching outputs of the control unit, the output of the switch is connected to the input of the first digital-to-analog converter and to the information input of the magnetic tape drive, the output of which is connected to the pulse inputs of the control unit and the magnetic tape drive and to the first input of the seventh element And, the output of the second square-wave generator is connected to the first input of the eighth element And, the output of the third square-wave generator is connected to the first input of the ninth element And and by the input of the control unit, the second inputs of the seventh, eighth and ninth AND elements are connected respectively to the first, second and third outputs of the output resolution of the control unit, the initial state setting output of which is connected to the second inputs of the second and third OR elements, to the setting inputs of the address counter and counter pulses, the output of the one-shot is connected to the second input of the tenth element And, the output of the pulse counter is connected to the information input of the address counter and the signal input of the control unit, the signal output The motion block of the control unit is connected to the input of the motion control of the drive on the magnetic tape, and the control unit contains two triggers, an AND element, a reverse counter, an indicator, a reference voltage setting unit and a mode switch unit, the outputs of which, from the first to the eighth, are respectively the outputs of the installation the initial state of the analysis signal, the first, second and third inputs of output resolution, the first, second and third switching outputs of the control unit, the installation output of the switch mode node soy inen with single inputs of the first and second triggers, the zero inputs of which are connected to the first output of the mode switch assembly, the synchronizing input of the first trigger is connected to the overflow output of the reverse counter, the installation input of which and the synchronizing input of the second trigger are connected to the input of the co-generation pulse of the control unit, which sums 13 input the reverse counter is connected to the output of the element And, the output of the first trigger is connected to the first input of the element Inc to the output of the motion signal of the control unit, second and third inputs of AND gates respectively connected to an inverted output of the second flip-flop and a clock input of the control unit, the indicator signal is input WMOs ~ 5 is the control unit house, the output of the threshold voltage setting unit is the threshold voltage output of the control unit. Figure 1 FIG. I 120681i Fi ?. 3