SU1201821A2 - Stabilized voltage converter with protection - Google Patents

Abstract

STABILIZED NORMAL VOLTAGE PROTECTION VOLTAGE WITH AUTHOR. St. No. 1141391, characterized in that, in order to increase functional reliability by increasing the number of converter re-inclusions with a slight interruption between successive overloads, the overload pulse driver is provided with an additional output, which through the added diode and the third integrating circuit is connected to the second element input And an additional reclosing unit, while the charge time of the third integrating circuit should be less than the charging time of the second integrating circuit. chains, and the time of its discharge should exceed the duration of the dead time of the transducer.

Description

00 N3

The invention relates to converter equipment and can be used in the development of secondary power sources.

The purpose of the invention is to increase the functional reliability by increasing the number of re-inclusions of the converter with a slight interruption between the next, one by one, overload.

FIG. 1 shows the structural scheme of the proposed stabilized voltage converter with protection; in fig. 2 and 3 - timing charts of the protection unit.

The converter contains a clock pulse generator 1 connected to the input of the counting trigger 2 and the input of a pulse-width modulator (PWM) 3, the second input of which through the feedback node 4 is connected to the output of the rectifier with a filter 5 installed at the output of the power amplifier 6, the control inputs of which are connected to the outputs of two logical elements AND 7 and 8, the first inputs of which are connected to the outputs of the counting trigger 2, the second combined inputs to the output of PWM 3, and the third combined inputs to the output of the OR-HE element 9 of the protection unit 10,which contains the shaper 11 of the overload pulses, to the first output of which is connected the second integrating circuit on diode 12, capacitor 13 and resistors 14 and 15, and to the second output - diode 16 and a third integrating circuit on capacitor 17 and resistor 18; A shaper 19 of overvoltage pulses through a first integrating circuit on a capacitor 20 and a resistor 21 is connected to the first input of the OR element 22 of the main reclosing unit 23, the other input of which is connected to the output of the logic element AND 24. The output of the logical element or 22 is connected to the first input of the OR element -NOT 9, with the first input of the logical element OR 25 of the additional reclosing node 26 and with the first input of the logical element AND 27. The first input of the AND element 24 is connected to the output of the logical element NOT 28 of the node 29 logical A common delay, whose input through diode 30 and time specifies an integrating circuit on resistors 31 and 32 and capacitor 33 is connected to the output of the element OR 25, the second input of the element AND the first input of the AND 34 logic element, the other input of which is connected through the third integrating chain and diode 16 to the second output of the driver 11 pulse overload. The second input of the logic element OR 25 is connected via the second integrating chain to the first output of the imaging unit 11 overload pulses, the second input of the OR-NOT 9 element and the first input of the logic element 35 of the logical memory node 36.

the other input of which is connected via the second integrating chain to the output of the additional reclosing unit 26. The output of the logical element AND 35 is connected to the first input of the logical element OR 37, the second input of which is connected to the output of the logical element AND 27, and the output with its third input and the third input of the element OR NOT 9.

The device works as follows.

When the supply voltage is applied to the inputs of the OR-NOT 9 element, there are no high logic levels. At its output, logical 1 is formed, which gives

permission to pass pulses from the paraphase outputs of the counting trigger 2 to the first inputs of logic gates And 7 and 8 and from the output of PWM 3 to their second inputs. The output AC voltage of the power amplifier 6 is converted into a constant rectifier with a filter 5 and fed through the feedback unit 4 to another input of the PWM 3, ensuring a corresponding change in the width of its output pulses. When an overload occurs at the separate outputs of the driver 11 for the overload pulses, high logic levels appear. At the same time, the parameters of the second and third integrating circuit are selected in such a way that logical 1 at the input of the AND 34 element appears earlier,

 than the input of the logic element OR 25, and the presence of two separate outputs of the shaper 11 overload pulses excludes their mutual influence. Moreover, the shaper AND overload pulses can

be performed, for example, on two one-threshold comparators.

Logic 0 is formed at the output of the final control element OR-NOT 9. Logic elements AND 7 and 8 are locked. Simultaneously, from the first output of the shaper 11 of the overload pulses, a high logic level is fed to the input of the logic element 35 of the logical memory node 36, while the logical input 0 is stored at the other input. corresponding to a dead-end pause, the following switching on of the converter does not occur, then the capacitor 17 is discharged to the level of logic O and at the output of the logic element OR 25

0, a logical O occurs, which causes the immediate discharge of the capacitor 33 of the logical delay node 29. If, after a short period of time, an overload occurs again (Fig. 3), then the outputs of the overload pulse generator are high logic levels, and logical 1 will remain at the output of the AND 34 until the switch is repeatedly switched and does not charge. dits

to the level of logical 1, the capacitor 33. In this case, when the first output of the shaper 11 appears, high-level overload pulses at the output of the AND 35 logic element appear logical 1, which is fed to the input of the OR 37 logic element and fixes the inhibit circuit in the locked state .

After the occurrence of overvoltage, the converter is switched on once. If the inclusion happens on

if the overvoltage is not eliminated, then the re-converter will not turn on, since at the second input of the logic element And 27 there is a logical "I and the first pulse with

the output of the former 19 leads to the appearance at its output and output of the node 36 of a logical logic memory of a high logic level and fixation of the protection circuit in the locked state. The values of tp2 and tfj (Figs. 2 and 3) characterize the charge and discharge times of the capacitors of the second and third integrating circuits.

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Fig 2

Claims (1)

STABILIZED VOLTAGE CONVERTER WITH PROTECTION by ed. St. No. 1141391, characterized in that, in order to increase functional reliability by increasing the number of repeated starts of the converter with a slight break between consecutive overloads, the overload pulse shaper is equipped with an additional output, which is connected to the second input through an additional diode and a third integrating circuit element And additional node re-inclusion, while the charge time of the third integrating circuit should be less than the charge time of the second integrating circuit, and the time of its discharge should exceed the duration of the current-free pause of the converter. >