SU1193821A1 - Frequency-to-digital converter - Google Patents

Abstract

A FREQUENCY CONVERTER containing a twigger, the first output of which is connected to the first key input, a pulse generator, the first output of which is connected to the second key input, the output of which is connected to the counting input of the pulse counter, the first OR element, the output of which is connected to the first setting input of the pulse counter, and the first input is combined with the first input of the second OR element, which is different in purpose. extending the functionality by providing control, the first, second and third pulse formers, an additional counter, a failure trigger, an overflow trigger, the first, second and third control triggers are introduced into it, and the control input of the third control trigger is connected to the second trigger output, counting input - with a different output of the pulse generator. and the output with the counting input of the failure trigger and the input of the first pulse generator, the output of which is connected to the counting input of the trigger, the second installation input of the pulse counter, the first input of the first OR element and the control input of the first control trigger, the first output of which is connected to the second input of the second the OR element, and the second output - with the control input of the overflow trigger, the counting input of which is connected to the overflow output of the pulse counter and combined with the input of the second pulse former, output one of which is connected to the second input of the first OR element and to the counting input of the first control trigger, the output of the second OR element is connected to the control inputs of the additional counter and the second control trigger, the counting input of which is connected to the output of the additional counter, and the output to the control the failure trigger input, the key output is connected to, the counter input of the additional tC counter, the control input of the trigger signal is connected to the output of the third pulse generator, whose input is the input of the transducer l, the pulse counter outputs trigger rejection, overflow and trigger the third control trigger are. converter outputs.

Description

The invention relates to automation and can be used to convert the output signal of a frequency sensor.

The purpose of the invention is to enhance the functionality by ensuring control of the input signal parameters and control of the correct functioning of the device.

The drawing shows an block diagram of the converter frequency-code.

The device contains the first pulse shaper 1, a trigger 2, a key 3 controls the trigger 4, a pulse generator 5, a pulse counter 6, a second pulse shaper 7, an additional counter 8, the first element OR 9, the first control trigger -10, the second element OR 11, the second control trigger 12, the failure trigger 13, the overflow trigger 14, the third pulse generator 15, whose input is the input 16 of the frequency converter, the outputs 17.

The first output of the trigger 2 is connected to the first input of the key 3, the second input of which is connected to the first output of the generator 5, the second output of which is connected to the counting input of the third control trigger 4, the control input of which is connected to the second output of the trigger 2, the output of the trigger 4 is connected the input of the driver 1, the counting input of the trigger 13 and the bus 17 .. The output of the key 3 is connected with the counting inputs of the counter 8 and the counter 6, the output of which is connected to the control input of the trigger 14 and the input of the former 7 is connected tothe output of element 9, and the second setup input is combined with the first inputs of elements 9 and 11, the counting inputs of flip-flops 2 and 10 and connected to the output of shaper 1. The output of shaper 7 is connected to the second input of element 9 and controlled by the input of trigger 10, the first output of which The second input is connected with the second input of the element 11, and the second with the counting input of the trigger 14. The output of the element 11 is connected to the control inputs of the counter 8 and the trigger 12, the output of which is connected to the control input of the trigger 13, and the counting input to the output of the counter 8i Shaper output 15, entrance to is expensive

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input 16 of the converter is connected to the control input of trigger 2, and outputs of the counter 6, triggers 13 and 14 are connected to the outputs 17.

5 The frequency code converter works as follows.

When the supply voltage is turned on, the converter is reset. Input signal

10 16 in the form of alternating voltage is converted into short pulses by means of a driver 15 pulses. .

The pulse from the driver 15 sets the trigger 2 to the state O, which prohibits the passage of the pulses of the reference frequency from the generator 5 through the key 3 to the counting input of counter 6 and finishes the conversion

20 of the previous measurement period. The code recorded in counter 6 is the result of measuring the previous period and arrives at output 17. From the second output of trigger 2, a signal is sent to the control input of trigger 4, allowing it to function under the action of generator pulses 5. Trigger 4 with the arrival of the first pulse on its calculating

30, the input changes from state Q to state Q. In this case, the signal, for example, in the form of a logical 1, is output to output 17. On the leading edge of this pulse, the state changes

c trigger 13 (only if there is an enable signal at its input from trigger 12, which appears when counter 6 fails). In the presence of a signal in the form of a logical 1 with a trigger 0 R3 outputs 17, the contents of counter 6 are transmitted ...

The second pulse of the generator 5, after the termination of the operation of the counter 6, translates the trigger 4 from

5 Q states to Q state, while on the falling edge of the signal from the Q output, the shaper 1 generates a pulse that sets the counter 6 directly and through the OR element 9 to the state 1, the triggers 10 and 12 and the counter 8 - to the initial state trigger, and trigger 2 to state 1, starting a new transformation. In this case, the signal from trigger 2 is prohibited

- the operation of the trigger 4 under the action of the pulses of the generator 5.

After trigger 2 is set to state 1, generator 5 pulses

through the key 3, they arrive at counter 6 and additional counter 8. Under the action of the first pulse at the output of counter 6, we obtain a change in the signal, for example, from logical 1 to logical O, which affects trigger 14 and driver 7. Trigger 14 does not change its state due to the presence of a inhibitory signal from trigger 10 at its second input, and driver 7 generates a pulse that transfers trigger 10 from state 1 to state O. Moreover, after transition of trigger 10 from state 1, in the state O, it becomes self-blocking and does not respond to pulses from the former 7. In this case, the trigger 10 receives a second signal at the second input of the trigger 14, allowing it to function when the overflow signal of the counter 6 reappears during the conversion period and the input frequency. From trigger 10, through the element OR 11, the installation inputs of trigger 12 and low-level counter 8 receive a signal that sets trigger 12 to its initial state and inhibits the activation of small-size counter 8. From the output of trigger 12, the control input of trigger 13 receives a signal prohibiting the transition to the state of forming a failure signal under the action of pulses coming from the trigger 4. The presence of the inhibit signal at the control input of the trigger 13 from the output of the trigger 12 indicates that the counter 6 is functioning correctly. When counter 6 goes from state t to state O, it begins to accumulate stable frequency pulses from key Z.Eslr, the number of pulses received during the measured period is less than counter capacitance 6, then no overflow occurs, and a code proportional to the period of the input frequency. If the number of incoming pulses for a period larger than the counter-meter 6, then an overflow pulse appears again at the output, which affects the trigger 14, transfers it from the state 0 | in state 1 (at the second input there is an enable signal). With the release of trigger 14 together with the registered

the counter 6 with the code at the outputs T7 receives a signal indicating a registered code that does not correspond to the measured period of the input frequency. Distorted measurement result is excluded from processing.

The appearance of the signal at the output of the trigger 14 indicates that the period of the input signal is out of the allowed value specified for this converter. The trigger 10 under the action of the second pulse from the driver 7, as a result of the second overflow of the counter 6, does not change its state, since after the first pulse it becomes self-locking. After the conversion of the input frequency cycle, the cycle of performing the control operation and resetting the converter to the initial position for measuring the next n + 1 period of the input frequency is repeated. If in the n + 1-M cycle of conversion of the period of the input frequency under the action of the first pulse coming from the key 3, the counter 6 does not change its state, i.e. does not go from state 1 to state O, therefore, at the output of counter 6, a pulse indicating a change in the state of counter 6 from 1 to O does not appear. Then trigger 10 does not change its state, and. from its output through the element OR 11, a signal is received, allowing the further operation of the low-level counter 8 and the trigger. 12 when the counter overflows 8. The capacity of the counter 8 is chosen such that it overflows later when the inhibit signal from the trigger 10 functions. When the counter 8 overflows, the counting input of the trigger 12 receives a signal that sets it to state 1. And when changing from O in state 1, trigger 12 is set to self-blocking and does not function under the action of the next overflow signal coming from a low-level counter 8. From trigger 12 to control input of trigger 13 a signal arrives its operation under the action of the signal from trigger 4. Since the output of counter 6 does not receive a zero signal, the number in the counter b is not corresponding to the actual value of the period of the input frequency. When a signal appears from the output of flip-flop A, the flip-flop 13 changes from state 1 to state O, since there is a signal at the control input permitting its operation. The transition of the flip-flop 13 from the state 1 to the state O indicates 11938 5 О 21 that a failure occurs in the counter 6. From the output of the trigger 13, a signal, for example, in input of a logical O, enters the processing device and eliminates the processing of the code recorded in the counter 6. Thus, the distorted result registered in the counter 6 is excluded from the processing in the presence of at least one prohibitory signal from the outputs of the flip-flops 13 and 14.

Claims (1)

FREQUENCY CONVERTER, 'containing a trigger, the first output of which is connected to the first input of the key, a pulse generator, the first output of which is connected to the second input of the key, the output of which is connected to the counting input of the pulse counter, the first OR element, the output of which is connected to the first installation input a pulse counter, and the first input is combined with the first input of the second OR element, characterized in that, for the purpose. expanding functionality by providing control, the first, second and third pulse shapers, an additional counter, a failure trigger, an overflow trigger, the first, second and third control triggers are introduced into it, and the control input of the third control trigger is connected to the second output of the trigger, the counting input is with another pulse generator output. and the output is with the counting input of the failure trigger and the input of the first pulse shaper, the output of which is connected to the counting input of the trigger, the second installation input of the counter \ pulses, the first input of the first OR element and the control input of the first control trigger, the first output of which is connected to the second input of the second element OR, and the second output with the control input of the overflow trigger, the counting input of which is connected to the overflow output of the pulse counter and combined with the input of the second pulse shaper, the output of which connected to the second input of the first OR element and to the counting input of the first control trigger, the output of the second OR element is connected to the control inputs of the additional counter and the second control trigger, the counting input of which is connected to the output of the additional counter, and the output to the control input of the failure trigger, output the key is connected to the counting input of the additional counter, the control input of the trigger is connected to the output of the third pulse shaper, the input of which is the input of the converter, the outputs of the counter Single pulse, failure trigger, trigger the overflow, and the third control are trigger. converter outputs. > ^eleven