SU1193816A1 - Travel converter - Google Patents

Description

The invention relates to automation and computing and can

be used to convert

angular or linear displacement

in digital code.

The purpose of the invention is to improve the accuracy of the converter.

FIG. 1 shows a block diagram of a displacement transducer to a code; in fig. 2 - diagrams explaining the operation of the device.

The converter contains a generator 1, the main divider 2 frequencies, including a scaling divider 3 frequencies and a reference divider 4 frequencies, additional dividers 5 ^ - 5 _P frequencies, each of which has a scaling divider 6 'frequency and a reference frequency divider 7', shaper 8 pulses, phase splitter 9, phase shifter 10, quantizer 11, output register 12, code bus 13, counter 14 pulses, distributor 15 pulses, registers 16, -16 ", adder 17, unit 18 of code, link 19 kinematic connection, moving mechanism 20.

The Converter operates as follows.

The clock pulses are delivered from the first output of the generator 1 (Fig. 1) to the counting inputs of the main 2 and additional 5 ^ –5 ^ frequency dividers.

The main frequency divider 2 generates code sweep signals (Fig. 2 c), which are fed to the input of shaper 8 pulses and phase splitter 9. Of these signals, phase splitter 9 produces a two-phase or three-phase supply voltage system for the phase shifter

10 types of rotating transformer or selsyn. At the output of the phase shifter 10, a signal is generated whose phase shift relative to the reference signal (FIG. 2 £) —one of the phases of the power supply of the phase shifter 10 — is proportional to the angular movement of the phase shifter 10, and hence to the movement of the mechanism 20 connected to the shaft of the phase shifter 10 through link 19. This signal (Fig. 2b) is fed to the first input of the quantizer 11. To the second input of the quantizer

11 impulses come from the second output of the generator 1, which are used 93816

They are called for phase quantization of the output signal of phase shifter b. At the second output of quantizer 11, narrow quantized 5 phase pulses are formed (Fig. 2?), whose frequency depending on the direction of rotation of the shaft of the phase shifter TO is lower or higher than the frequency of the reference signal (Fig. 25).

10 The phase-quantized pulses (Fig. 2d) come from the output of the quantizer 11 to the input of the register synchronization 16 (-16 _P. ) The information inputs of the registers 16 _η -16 "are received from the outputs of the additional dividers 5, -5 _{n of} the code sweep signals ( Fig. Synchronized signal zeroing.

Signal zeroing additional

20 dividers 5, -5 _p frequencies are produced by a group of elements containing a shaper of 8 pulses, a counter of 14 pulses and a dispenser of 15 pulses. Shaper 8 pulses

25 generates a pulse at the moment it arrives at its input from the output of the main divider 2 of the frequency of the code combination corresponding to the origin of movement. Formari impulses

30 of the receiver 8 are counted by the counter 14, the output code of which controls the distributor 15, which generates a pulse at the ΐth Output at the moment when the counter 14 switches to the state corresponding to the number ί.

In the diagrams of FIG. 2 <}, e, * shows the type of code sweeps generated by additional dividers

5 ,, - 5 _n frequencies with n = 3 and the generation of nulling signals at a zero code combination in the main divider 2 frequencies. As can be seen from the diagrams, the period of code sweeps of additional dividers

4 $ 5 _< –5 _P frequencies η times (in this case three times) more than the reference frequency period (Fig. 25), and the beginnings of the code sweeps are offset relative to each other by the reference period

₅₀ beeps.

The maximum code value that is fired by additional dividers of 5, -5 _P frequencies is equal to the number of displacement increments M, 55 per revolution of the shaft of the phase shifter 10

At the moment of arrival from the second output of the quantizer, 11 quantized by

The phase of the pulses (Fig. 2d) at the input

one

the synchronization of the intermediate registers 16, - 16 _P into them are transferred from the additional dividers 5, -5 „frequency codes C (Fig. 2 ^, and, k):

where - the angle of rotation of the shaft of the phase shifter 10 within one revolution relative to the position adopted for the origin.

Codes b, ', recorded in registers • 16, -1b _p , are stored in them almost

during the period of the output signal (FIG. 26) of the phase shifter 10. From the outputs of registers 16 ^ - 16 _{and the} codes are fed to the summation inputs of the adder 17. As a result of the summation of [These codes, the code is obtained (Fig. 2 l),

p-ι

_Μ „ _{Μ +} _Μ _?

containing a constant component

B - - ^{t 0} 2

chen dashed line.

The value of the code b _o is typed in the unit 18 of the code and is fed to the input of the subtraction of the adder 17, the output of which forms the code

c

B = y-M (Fig. 2m), corresponding to

the amount of movement of the mechanism 20 associated with the shaft of the phase shifter 10 through the link 19.

Code b is written to the output register 12 by pulses arriving at the synchronization input from the first output of the quantizer 11 and delayed relative to the pulses at the first output of the quantizer 11 for a time that is in FIG. 2n from193816 ⁴

walkable to perform arithmetic operations in the adder.

The code (fig. 2m), fixed in register 12, is fed to the code

5 bus 13.

Thus, the output code of the transducer is formed from n code values selected by phase-quantized pulses from n code codes

10 sweeps, obtained with the help of n additional dividers 5, -5 „frequency, reset to n times lower than the frequency of the reference signal.

Moreover, the number of discrete πει 5 displacements M per one

rotation of the shaft of the phase shifter 10, is equal to ί * ι

M =, where £ *, is the signal frequency

output scaling divider 6 ;, frequency; £ ₀ is the frequency of the zeroing signal of the additional divider 5 frequency.

ί _Γ with - ^ op

20

Since £ _m = £

TO,

25

Where

thirty

35

ίοπ ^K MG

pulse frequency at the first output of the generator 1; reference frequency; the division ratio of the scaling divider frequency 6;

the division ratio of the scaling divider 3 frequency;

Cd - the division ratio of the reference divider 4 frequency

40

and .. To m "2

then in this device M = ~ - K.,.

^k * m / _s

This expression shows that the degree of correspondence of the output transducer code to the actual movement of the mechanism 20 depends on the accuracy

tasks of Κ _Μί and

* ±

Claims (1)

MOVING CONVERTER TO CODE, containing a generator, the first output of which through serially connected main frequency divider, phase splitter and phase ^-1 inverter is connected to the first input of the quantizer, the first output of which is connected to the synchronous input of the output register, the output of the main frequency divider is connected to the input of the pulse shaper, The first "generator output is connected to the counting input of the first additional frequency divider, characterized in that, in order to improve accuracy. converter, η additional frequency dividers, pulse counter, pulse distributor, registers by the number of additional frequency dividers, adder and code adjuster are entered into it, the output of the pulse shaper is connected to the input of the pulse distributor through the pulse counter, each output is ^; It is connected to the synchronous input of the corresponding additional frequency divider, the outputs of the additional frequency dividers are connected to the information inputs of the corresponding registers, the outputs of which are connected to the summing inputs of the adder, the output of which is connected to the information input of the output register, the output of the code setter is connected to the reading one. adder input, the second output of the generator is connected to the second input of the quantizer, the second output of which is under - * keys to the synchronous inputs of registers, the first output of the generator is connected to the counting inputs η of additional frequency dividers. 918861G ^{, P} > I. 11