SU1188893A1 - Device for transmission of information with error protection - Google Patents

Abstract

TRANSMISSION DEVICE WITH PROTECTION AGAINST ERRORS, containing serially connected synchronizer, pulse distributor, block of key elements and analog-to-digital converter, as well as shift register, block of elements And and the generator of the reference code, the input of sync pulses of code groups of which are connected to the output of the synchronizer, and the inputs of the block of key elements and the output of the shift register are, respectively, the inputs and output of the device, characterized in that, in order to increase the reliability of messages with interference leading to threefold and fourfold errors, the block of elements OR, the block of modulo two adders and an additional modulo two adder are entered, with M outputs of the analog-digital converter connected to the corresponding first information inputs of the shift register, M first inputs a block of adders modulo two and to the N inputs of an additional adder modulo two, the input of human clock sync generator of the reference code is connected to the output of human clock synchro pulses The pulses, direct and inverse outputs of the generator of the reference code are through the element block (Lite and block of OR elements are connected to the corresponding N second inputs of the modulo adders block two, the direct and inverse outputs of the additional modulo adder two are connected respectively to the combined second inputs and to the combined third inputs of the unit 00 00 00 cops And, and the N outputs of the block from the Mmators Modulo two are connected to the corresponding second informational and social inputs of the shift register, the clock input of the analog-digital converter zovatel combined with the input pulse distributor, and a shift register clock input connected to the output of the synchronizer.

Description

one

The invention relates to telecommunications and can be used in information transmission systems for error protection.

The aim of the invention is to increase the reliability of transmitted messages with interference resulting in triple and fourfold errors.

Figure 1 shows the structural circuit of a device for transmitting information with protection from. errors, FIG. 3 shows a structural electrical circuit of the reference code generator, FIG. 3 shows timing diagrams that explain the formation of frame sync pulses.

The device for transmitting information with error protection contains a pulse distributor 1, a block of 2 key elements, an analog-digital converter (ADC) 3, regis 4 shifts, a synchronizer 5, a reference code generator 6, a unit 7 modulo-two adders, and an additional modulator 8 two, a block of elements AND 9 and a block of elements OR 10.

The generator 6 of the reference code contains an inverter 11, the first 12 and the second 13 elements AND, the first elements OR 14 and the second elements OR 15.

An error-proof transmission device works as follows.

The pulse distributor 1 (Fig. 1) forms N sequences of switching pulses shifted along the time axis relative to each other by the value of kTu, where f, is the channel interval duration, k 1,2 ... These pulses alternately unlock the key elements of the block 2 key elements , the second inputs of which are input signals S. (tp). The signal samples are sequentially input to the ADC 3, where N-valued information binary words are generated. These code words are fed to register 4, where they are written on its odd cells, as well as into unit 7 modulo-two adders and an additional modulo-two adder. The modulo-two adders block 7 consists of N independent modulo-two adders, for one

888932

From the inputs of each of which, a binary O or 1 from A1DP 3 is fed in binary, and the other is sprinkled with direct or FF {a vertical 5 reference code from the generator 6 of the reference code. If the sum modulo two information tossings of the a | -discharge code A1DP 3 is O,

P 10 Ie ®Zlo: 0 then from the inverse output

Additional adder 8 modulo two to the first inputs N of the corresponding elements AND of the block of elements And 9 is fed 1, and sent to their second inputs are the send of the direct reference code, taken from the direct outputs of the generator 6, are fed to the second inputs of the corresponding elements OR of the block of the elements OR 10. The first inputs of these elements OR are given signals from the outputs of other elements of the AND 9 block of elements if their first inputs receive a signal 1 from the direct output of the additional adder 8 to

module two. This happens if

P (.

i (

In this case, the first inputs of the OR elements of the OR 10 block of cells are fed to the corresponding parcels of the inverted reference code taken from the inverse outputs of the generator 6.

5 At N outputs of the block of adders 7 modulo two, signals С are formed ;; or with; a, (,; where and informational elements of the N-bit one produced by ASCh1 3 ,,

0 b; and bj are the elements of the direct and inverted reference code. The reference code generator 6 employs forward and reverse reference codes for group and

5 frame sync. During the (N-I) -channel intervals, it forms code combinations for group synchronization. Within one channel interval,

0 for example the first, the duration of which

T -1

to N;

5 where T is the frame duration,

N is the number of channels

framing code words are formed. 31 The block diagram of generator 6 (FIG. 2) corresponds to the forward code of group synchronization 1010011 (reverse code 0101100), and for frame synchronization, the block diagram of generator 6 corresponds to direct code 1100101 (reverse code 0011010). To generate personnel signals from the second output of the pulse distributor 1 (Fig. 1), a sequence of pulses (Fig. 3b) with a power T and a following period Tjj is input to the input of generator 6, and a synchronization pulse (Fig. 3o) with frequency following words (code groups). At the output of the second element I 13, as a result of acting on its input of two sequences, a sequence of short impulses 1 ow is formed with the following frequency F - (FIG. 3) equal to the frame repetition rate. e of the first element And 12 a sequence of short pulses is formed with the frequency of following the words, from which the pulses, for example, of the 1st channel are removed (Fig. 3 {). And during the 1st channel interval, the generator 6 generates a parallel reference code 1100101 and 0011010, which serves for frame synchronization, and during the rest (N-O-channel intervals, the code .1010011 and 0101100 is formed. Thus, the ADC 3 generates information N - Digit Code Codes binaries that are written in the first N (e.g., odd) cells of register 4. These code words are also sent to an additional adder 8 modulo two and cnmmatmator unit 7 modulo two, to the second N inputs of which feed the direct or reverse code frame: howl or group sync. In block 7 modulo-2 adders, an N bit word C (, Cj, ..., Cp) is formed, each element of which is the result of modulo-adding two information elements a- and an element of the reference 188893 which is in sync with st from ( The code word a bili, .., S., is written in the N cells of register 4. From the country is a 2M-value word for reading impulses from the controller 5, and in succession form is fed to the output of the information transfer device with closed errors. Next, through the modulator, the There is a communication analogue. In the communication code transmitted through the channel, the reference code is stored in the reference code, so during the transmission the following Ianta are possible:; © ь ;,; ® - elements of the forward group synchronization code, - elements of the reverse group synchronization code, -. the elements of the direct frame synchronization code, are the elements of the reverse frame synchronization code, and the receiving side performs the following operations:.,., g (L; (), and - information elements allocated at the detector output, received elements C elements of the restored reference code elements reference code generated by a local generator. ,, - n + 1 If for odd n hj with even n, where h is the go level, it generates a signal of $ 2 O, and a direct code b is taken from the local reference code generator (receiving side), then Sg 1 and from the local generator reference code without reverse count b, b, ..., b i ,.

An elemental comparison is made of the restored reference code and the code of the local reference generator: ode and signals are generated; B; © bj. The sum Sj © S | is calculated.

If, when analyzing the received word, it turns out that something is the sum of odj 1 or / 3 1, then the code word is subject to rejection, since the word has an error of a certain multiplicity.

In the table: possible error variants of different multiplicity are given.

Multiplicity

a-, errors

g 1

X

X

Xx

Xx

 2

Xx

X x

Xx

.XX XX X

 3 X XX

X x x x x x

Xxxx

XXX.X

XXX

XXX

Xxxx

 four

Xxxx

The table shows that some of the multiplicity errors are not detected.

g

The number of these errors is N s.

The probability of undetectable errors is C. p, where p is the probability of distortion of the binary premise.

For example, with n 11 (reference code - Barker code), p

".-C;, M5 5.540-,

for a prototype

.five

ten

1 U, I vJ

Note

one

about

one

one

one

about

one

one

one

one

one

about

one

about

one

one

about

oh oh

about

Not detected

one

1 about 1

1 1 1

about about 1

Table continuation

. 2

i

t

Claims (1)

ERROR-PROTECTED INFORMATION TRANSMISSION DEVICE comprising a synchronizer, a pulse distributor, a block of key elements and an analog-to-digital converter, as well as a shift register, a block of elements And and a generator of a reference code, the input of the clock pulses of the code groups of which are connected to the output of the synchronizer, and information the inputs of the block of key elements and the output of the shift register are respectively the inputs and outputs of the device, characterized in that, in order to increase the reliability of the transmission messages in case of interference leading to triple and quadruple errors, the block of OR elements, the block of adders modulo two, and the additional adder modulo two are introduced, while N outputs of the analog-to-digital converter are connected to the corresponding first information inputs of the shift register, первым the first inputs block adders modulo two and N inputs of the adder modulo two, the input of the frame clock of the generator of the reference code is connected to the output of the frame clock of the pulse distributor, direct e and inverse outputs of the reference code generator through the block of elements AND and the block of elements OR are connected to the corresponding N second inputs of the block of adders modulo two, the direct and inverse outputs of the additional adder modulo two are connected respectively to the combined second inputs and the combined third inputs of the block of elements And, and N outputs of the adder block modulo two are connected to the corresponding second information inputs of the shift register, the clock input of the analog-to-digital converter is combined with the distribution input pulse generator, and the clock input of the shift register is connected to the output of the synchronizer. 00 □ o □ o so