SU1185312A1 - Device for controlling positional drive - Google Patents

Description

The invention relates to electrical engineering and is intended for use in positional drives.

The purpose of the invention is to improve the accuracy of the device.

On the fit. 1 is a block diagram of the device; in fig. 2 - functional diagrams of the second speed sensor and the third unit of comparison; in fig. 3 is a functional diagram of the first comparison unit; in fig. 4 Examples of path-speed dependence:

a) - start-stop movement with the passage of each section of the path with different speeds, b) - the optimal trajectory of movement for positioning at point A; in fig. 5 - examples of possible dependencies of speed — path (A - positioning points, B - speed switching points, C - speed measurement point);

a) - the rate of deceleration of acceleration is less than the reference; b) - braking speed is greater than the reference, c) - positioning point A is achieved in two cycles.

The device contains a program setting block 1, a sensor 2 paths, a first comparison block 3, a controlled divider 4 frequencies, a pulse counter 5, a code 6 analogue converter, a second comparison block 7, a first speed sensor 8, a position actuator 9, a second speed sensor 10, the third block 11 comparison.

The second speed sensor 10 (Fig. 2) consists of a pulse counter 12, a pulse generator 13 and a register 14.

The third comparison unit 11 (FIG. 2) contains the first counter 15 of the path, the first memory block 36, the first counter 17 of the address, the adder 18, the first element AND 19, the element NOT 20 and the second and third elements 21 and 22.

The first comparison unit 3 (FIG. 3) has a second track counter 23, a third 24 and a second 25 memory blocks, a reversing pulse counter 26, a second address counter 27, an element. OR 28, third address counter 29, fourth memory block 30.

2

The device works as follows.

According to the signal from block I of the program’s task, the starting address is set in block 11 of the comparison in the counter 17 of the address, in block

5 3 comparisons in counters 27 and 29 addresses. The counter code 27 addresses from the memory block 25 selects the most significant digits,;, and from the memory block 24, the lower digits of the inverse distance code to the first switching point.

The code received from the memory blocks 25 and 24 is recorded in the counter 23 of the path, in addition, the code from the memory block 24 is recorded in the reversible counter 26 for further possible correction. The signal from the output of the counter 23

15, arriving at the information input of the drive 9, causes it to move at a speed determined by the dividing coefficient code of the memory block 30. The pulses from the output of the sensor 2 paths are fed to the input of the counter 23 pu <

20 tees Upon reaching point B (Fig. 5), the output of the counter 23 of the path is an active signal “0” of the counter of the path ^ which adds one to the counters 27 and 29 of the address, thereby causing entry to the counter 23 of the path

25 coordinates of the new switching point, and at the output of memory 30 - the new value of the division factor. The pulses from the sensor 2 through the divider 4 are fed to the input of the counter 5. The digital output signal from the output of the counter 5 is converted in the converter 6, for example, into analog form when using a tachogenerator DC as the sensor 8. The differential signal appearing at the output of the comparator unit 7 is the control signal of the drive 9. The braking process begins. Thus, when the next switching point is reached, a new value appears at the output of the first comparison unit 3

dF code division factor.

In addition, the signals from the sensor 2 paths arrive at the input of the speed sensor 10, where

instantaneous speed is generated, and

also in the third block 11 comparison to the input

track counter where the reverse has been entered

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checkpoint coordinate code C

(Fig. 5d).

In the upper graph of FIG. 5 the solid line shows the dependence obtained in the current cycle (the dotted line in the previous _5- le), in the lower graph it is corrected in the subsequent cycle.

When the checkpoint C is reached, the signal ”0” of the track counter 15 appears, which, adding one to the address counter 17, calls the new coordinate of the control point from the memory block 16 and records this new value in the track counter 15. The signal “0” of the counter 15 of the path also allows comparison of the speed coming from the sensor 10 and the reference speed 45 set at the third output (”C”) of the memory block 16. At the output of the adder 18 a transfer signal appears if the code of the measured speed is less speed code 20

Element And 19, the output of which prohibits the signal only when the codes (at the output of adders 18 - all "1"). prohibits the passage of the signal "More" or "Less" on the output of block 11 comparison. The signal “More” or “Less”, acting on the control inputs of the reversible 26 counter, changes the low order bits of the switching point B by one, which corresponds to the elementary error &. Signal “More” or “Less”

writes to the memory unit 26 the corrected low-order code of the switching point coordinates.

Thus, in the next positioning cycle, the coordinates of the switching points are adjusted by a value of 5 to obtain the required positioning accuracy. If the magnitude of the error is greater than δ is the elementary positioning error, then the correction of the switching point will occur in a larger number of positioning cycles (Fig. 4c).

A positional drive with automatic control allows you to implement any forward-specified dependence of the phase coordinates of the path and velocity system and correct these relationships by comparing the measured and predetermined velocity values at the predetermined control points.

Fig 1

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With the benefit of the fiefdom 2.

tasks of aerograms ^ / phage. 2

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From sensor output 2

FIG. B

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Claims (4)

1 .. DEVICE FOR POSITIONAL DRIVE CONTROL, containing a program setting block, connected by an output to the first input of the first comparison unit connected by a second input to the output of a nougat sensor and information input of a controlled frequency divider, the first output to the information input of a positional drive, the second output - from the trigger input of the pulse counter, and the third outputs - with the installed inputs of a controlled frequency divider connected by an output to the counting input of a pulse counter connected by bit Outputs with the input of the converter codebook connected by the output to the first input of the second comparator unit connected by the second input to the output of the first speed sensor, and the output to the control input of the positional drive, which is characterized by the fact that a third block is entered into it to improve the accuracy of the device comparisons and the second speed sensor connected by the input to the output of the sensor of the path, and the output to the first input of the third comparison unit, the second input to the output of the program reference block, the third input to the output of the path sensor, and the outputs to the third inputs of the first comparison unit. 2. The device according to p. ^ Different ’in that the third unit of comparison contains the first track counter, connected the counting input with the third output of the third comparison unit, and the output with the control input of the adder and the counting input of the first address counter connected by the installed input to the second input of the third comparison unit, the fault input and bit outputs respectively to the first output and inputs of the first memory block connected the second outputs - with the installation inputs of the first track counter, and the third outputs - with the first inputs of the adder connected by the second inputs to the first input of the third comparison unit, the outputs - to the moves of the first element I, and the output “Transfer” to the first input of the second element and through the element NOT to the first input of the third element I connected to the output of the third comparison unit, and the second input to the output of the first element I and the second input of the second element And connected to the corresponding output of the third unit of comparison. 3. Device by π. 1 and 2, that is, the first comparison unit contains a second track counter connected by a counting input to the second input of the first comparison block, and an output to the counting inputs of the second and third address counters and the first and the second output of the first unit of comparison, the installation. the high-order outputs to the first outputs of the second memory block, and the low-level setting inputs to. the outputs of the third memory block and the installation inputs of the reversible pulse counter connected to the summing and subtracting inputs with the corresponding third inputs of the first comparison unit and the OR element inputs, and the bit outputs are the information input of the third memory block connected by the control 5 and 1185312 1185312 the input to the output of the element OR, and the address inputs to the address inputs of the second memory block and the bit outputs of the second address counter connected by the fault input to the second output of the second memory block and the fault input third> of the address counter connected by the setup input to the setup input of the second counter the address and the first input of the first comparison unit, and the bit outputs to the address inputs of the fourth memory block one '