SU1181148A1 - Angle-to-digital converter - Google Patents

Abstract

CONVERTER ANGLE OF TURNING. SHAFT B A CODE containing a pulse generator, the output of which is connected via a serially connected frequency divider, voltage form converter, power amplifier, phase shifter and first zero-body connected to the first input of the time range generator, the output of which is connected to the control input of the key whose output is connected to the summing input of the meter, the output of the power amplifier is connected to the input of the second null organ, and a memory device, characterized in that, in order to improve accuracy, reliability and simplicity and the converter, an encoder is entered into it, - a trigger and an element, whose output is connected to the subtractive input of the counter, the output of the pulse generator is connected to the first input of the encoder and the information input of the key, the output of the first zero-organ, the output of the second the zero-organ is connected to the third input (L of the encoder and the second input of the time interval imager, the first and second outputs of the encoder are connected to the inputs of the storage device, the output of which is connected to the first input of the And element, second second encoder output through D- flip-flop is connected to the second input member 4 IM 00 00

Description

I

The invention relates to automation and computing devices and can be used in converters of analog values into 1C-1FORM code, as well as for automatic input of information into an electronic computer.

The purpose of the invention is improving the accuracy and reliability of the converter, as well as simplifying its circuit,

The drawing shows a block diagram of the device.

The converter contains a pulse generator 1, a frequency divider 2 a voltage form converter 3, a power amplifier 4, a phase shifter 5, null organs 6 and 7, a time interval imager 8, a key 9, a counter 10, an encoder 11, a memory device 1 2, D trigger 1 item and 14.

The Converter operates as follows.

The pulses of the clock frequency produced by the generator 1 are fed into a divider 2 frequencies and, in the form of symmetric rectangular pulses, are applied to the converter 3 of the voltage form. The sinusoidal voltage from the output of the latter is amplified by the power amplifier 4 and fed to the phase shifter 5 as a reference, and from the output of the phase shifter 5 as a signal whose phase is proportional to the rotation angle of the rotor of the phase shifter 5. The reference and signal voltages are applied to the zero organs 6 and 7 , generating rectangular lines, the fronts of which coincide in time with the moments of zero crossing of the reference and signal voltages. The signals from the zero-organs 6 and 7 are fed to the inputs of the imaging unit 8, the pulses from the block whose sequence sequence is equal to the time shift between the reference and signal voltages, go to control the input of the key 9, to the information input of which the impulses of the generator 1 are fed.

The number of clock pulses transmitted through the switch 9 to the counter 10 is recorded therein as a code proportional to the angle of rotation of the phase shifter 5.

The beginning of the time interval of the driver 8, specified by the reference

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The signal from the zero-organ 6 is shifted relative to the pulses of the generator 1 due to the phase shift of the reference signal in the voltage form converter 3 and the amplifier 4. Since it is almost impossible to ensure the constant phase shift of these nodes in the temperature range and for a long time the mutual offset the beginning of the time interval and clock pulses leads to an error. The error of the mismatch of the end of the time interval with the pulses of the generator 1 also leads to the error.

When signals from the nullorgan 6 and the generator 1 in the encoder 11 arrive, the signal is converted into 1 or O depending on the duty cycle of the clock pulses of the generator 1 and they coincide with the pulses of the zero organs 6 and 7. The output signal O or 1 comes from the output of the cprato jpa 11 into memory 12, in which the state of the output signal of the encoder 11 is saved to the signal obtained by comparing the signals of the generator 1 and the zero-organ 7, B. As a result of the comparison, the O or 1 level is formed at the output of the encoder 11 simultaneously to the second input of the storage device 12 and D - the trigger 13, the outputs of which are connected to the element 14.

If the sim1-1etric rectangular pulses of the generator 1 do not match the signals of the zero organs 6 or 7, the signal 1 is not formed at one of the outputs of the encoder 11, which in turn does not provide the signal 1 at the output of blocks 12 or 13, as a result of the output of the AND element 14, a level O is generated which does not correct the received code. (

When the pulses of the generator 1 coincide with the signals of the zero organs 6 and 7, the outputs of the encoder 11 generate signals 1 at the output of memory 12 and JD flip-flop 13, which leads to the formation of 1 at the output of element I 14, with the result that the unit of the least significant bit decreases counter content 10.

The signal of circuit 14 is fed to the subtracting input of counter 10, where it subtracts the error from the measurement result obtained to the compensator.

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In the pre-branded scheme, the encoder 1 1. The inventive invention of the invention can consist of two elements of singing with the known AND V transducers, and the memory device provides a higher accuracy of 12 and 13 of the trigger 13 each on one vii destabilizing factors, and

trigger. also greatly simplifies the circuit.

Claims (1)

TURN ANGLE CONVERTER. VALA IN THE CODE containing a pulse generator, the output of which through a series-connected frequency divider, a voltage converter, a power amplifier, a phase shifter and a first zero-organ is connected to the first input of the time interval shaper, the output of which is connected to the control input of the key, the output of which is connected to to the summing input of the counter, the output of the power amplifier is connected to the input of the second zero-organ, and a storage device, characterized in that, in order to improve accuracy, reliability and simplify the conversion the browser, the encoder is inserted into it!! —the trigger and the And element, whose output is connected to the subtracting input of the counter, the output of the pulse generator is connected to the first input of the encoder and the information input of the key, the output of the first zero-organ is connected to the second input of the encoder, the output of the second zero -organ is connected to the third input of the encoder and the second input of the shaper of the time interval, the first and second outputs of the encoder are connected to the inputs of the storage device, the output of which is connected to the first input of the element And, the second output of the cipher ora through -? the trigger is connected to the second input element I. 1 1181148