SU1171817A1 - Device for averaging random pulse sequence - Google Patents

Abstract

A DEVICE FOR AVERAGING A RANDOM PULSE SEQUENCE, containing a pulse distributor, switches, a group of keys, an adder, a block of integrators, a pulse distributor input is a device synchronization input, the control inputs of the first switch and key groups are combined and connected to the first output of the pulse distributor, the second output which is connected to the control input of the second switch, the output of the second switch is connected to the input of the integrator unit, the output of which is connected to the information The primary input of the first switch is the output of the device, characterized in that, in order to increase accuracy, a block of storage capacitors is inserted into it, the first input of the dry.mmator is an information input of the device, the second input of the adder is connected to the output of the first switch, the output of the adder is connected with the input of the storage capacitor unit, the output of which (O ROG is connected respectively to the inputs of the key group and the second switch, you (L course of the key group is connected to the zero potential bus.

Description

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The invention relates to computing, is intended for processing random pulsed signals and can be used in equipment for detecting corrosion of underground pipelines by electromagnetic methods, in addition, the device can be used in field ,. s-of "zi; ke at aero electrical prospecting of minerals.

The purpose of the invention is to improve the accuracy of the hardware processing of random pulse signals.

The drawing shows the functional diagram of the device; in fig. 2 - pulse timing diagrams explaining the operation of the device.

The device contains an adder 1, a block 2 consisting of n storage capacitors, a distributor of 3 pulses, a group of 4 keys, a second switch 5, a block of 6 integrators, the first switch 7, the first input 8 of the device, the second input 9 of the device, the first output 10 and the second output 11 of the device.

The device works as follows.

The input 9 of the device enters a sign-alternating sequence of damped (for example, exponentially) pulses.

When a positive sync pulse arrives at the input 8, a sequence of n time-separated gate pulses is formed at the output of the distributor 3. At the moment of action of the first pulse of the sequence, the signal of positive polarity arrives at the first input of the adder, and the voltage of Ui from the output of the first integrator is sent to the other input of the adder via the first switch 7 key. As a result, voltage (t) - is generated at the output of adder 1, where KI is the voltage transfer coefficient of the adder across the signal input. Cg is the voltage transfer coefficient over the feedback input.

The voltage from the output of the adder is applied to the first plates of the storage capacitors. By the action of the first pulse of the sequence, the second plate of the first storage capacitor is connected via the first key of group 4 to the zero potential bus, and the first capacitor of unit 2 is charged before the output voltage of the adder. Consequently, at the time tt of the end of the first strobe pulse, the capacitor is charged before the voltage

UU, K, A, - KJ.UI,

where AI is the value of the input signal. Under the action of the second strobe-pulse of the sequence, the second plate of the second storage capacitor is connected to the zero potential bus, and the voltage Uj from the output of the second integrator is applied to the second input of the adder. As a result, at the time tj of the end of the second strobe pulse, the second capacitor of the unit 2 is charged before the voltage, A2 is KaUj, where Ag is the value of the input signal A (t) at the time of the end of the second strobe pulse.

0 Under the action of the third strobe pulse, the third capacitor of unit 2 is charged, etc.

at the moment tu of the termination of the nth strobe pulse, the nth capacitor of the unit 2 is charged before the voltage UtiE KiAti - KaU The maximum number of channels is selected from the condition Pdak BA

where in - the duration of information

pulses;

 - the duration of the strobe pulses. 0 Upon the arrival of a negative sync pulse, a sequence of strobe pulses is formed at the second output of the distributor 3.

When the first strobe pulse appears at the control input of switch 5, the second lining of the first storage capacitor of block 2 is connected via the first switch switch key 5 to the input of the first integrator of block 6. Because after a negative clock Q is received, a negative pulse is applied to the input of the adder A (t), then a voltage pulse, KiA (t), is generated at the output of the adder.

Consequently, the first capacitor of unit 2 during the action of the first strobe-pulse 5 is recharged to the integrator input from the voltage Uta to the voltage Uja - KiA (t), which at the time ti. (Tj ij) of the end of the first strobe pulse is determined from ratios.

As a result of the recharge of the first storage capacitor to the input of the first integrator consisting of a DC amplifier with an integrating capacitor in the negative feedback circuit, the integrating capacitor Ci-co5 is charged

dch AU, rCi-Ci KiAn-K, Ut (i-l) -bK, A ,, Aii-K2Ui (i-1), where Ci is the value of the capacity of the first capacitor of the unit 2;

AUii-change in the output voltage Ut (i) at the first integrating capacitor, with a capacity of Ct, 1,2,3, ...

When control 5 of the switch 5 receives a second gate-pulse, the second sequence, the second capacitor of block 2 is connected to the input of the second integrator of block 6 and the second integrator

Claims (1)

A DEVICE FOR AVERAGING A RANDOM PULSE SEQUENCE, containing a pulse distributor, switches, a key group, an adder, an integrator unit, a pulse distributor input is a synchronization input of the device, the control inputs of the first switch and key groups are combined and connected to the first output of the pulse distributor, the second output of which connected to the control input of the second switch, the output of the second switch is connected to the input of the integrator block, the output of which is connected to the information The first switch is the output of the device, characterized in that, in order to improve accuracy, a block of storage capacitors is inserted into it, the first input of the adder is the information input of the device, the second input of the adder is connected to the output of the first switch, the output of the adder is connected to the input of the block of storage capacitors , the output of which is connected respectively to the inputs of the key group and the second switch, the output of the key group is connected to the bus of zero potential. (/) FIG. 1