SU993473A1

SU993473A1 - Delay device

Info

Publication number: SU993473A1
Application number: SU813311459A
Authority: SU
Inventors: Валентин Павлович Сайчев; Олег Федорович Чепуренко
Original assignee: Предприятие П/Я Г-4598
Priority date: 1981-07-03
Filing date: 1981-07-03
Publication date: 1983-01-30

Description

Изобретение относитс к импульсной Технике и предназначено дл при-, менени в радиотехнической аппаратуре различного назначени .The invention relates to a pulse Technique and is intended for use in various types of radio equipment.

Известно устройство задержки, содержащее одновибратор, выполненный по схеме генератора фантастронного типа , фиксирующий диод, подключенный к коллектору одного из транзисторов одновибратора, источник фиксирующего напр жени , например ннтегрир шжций конденсатор, подключённый к источнику входных импульсов через эмиттерный повторитель и дифференцирующую цепь, а к фиксирующему диоду - через даугой эмиттерный повторитель l.A delay device is known that contains a single vibrator made according to a fadron type generator circuit, a fixing diode connected to the collector of one of the single vibrator transistors, a clamping voltage source, for example, a capacitor connected to the input pulse source through an emitter follower and a differentiating circuit, and to a fixing generator diode - through the emitter follower l.

Устройство сложно и имеет недостаточную точность.The device is difficult and has insufficient accuracy.

Наиболее близким к предлагаёмеому вл етс устройство задержки, выполненное на трехтранзисторном фантастр оне .Closest to the proposed device is a delay device made on a three-transistor fiction printer.

Длительность задержки в известном устройстве определ етс произведением сопротивлени врем эадающего резистора на емкость хронирумцего конденсатора , что не позвол ет сформировать задержку, пропорциональную количеству импульсов, поступивших на управл к ций вход фантастрона..The delay time in the known device is determined by the product of the resistance time of the matching resistor and the capacitance of the timed capacitor, which does not allow to form a delay proportional to the number of pulses received on the controls of the fadron input.

Цель изобретени - получение за- держки, пропорциональной количест-. ву импульсов, поступивших на управл ющий вход фантастрона.The purpose of the invention is to obtain a delay proportional to the amount of -. impulses received on the control input fadron.

Поставленна цель достигаетс тем, что в устр.ойстве задержки, содержащем фантастрон, выполненный на трех транзисторах п-р-п типа проводимости, хронирующа цепь выполн етс в виде The goal is achieved by the fact that in a delay device containing a fadron made on three transistors of the pn type of conductivity, the timing circuit is in the form of

10 емкостного накопител , содержащего нормирующий транзисторный каскад, включенный по схеме с общим эмит- тером между шиной питани и общей точкой схемы, коллектор которого10 of a capacitive drive comprising a normalizing transistor cascade connected in a circuit with a common emitter between the power bus and a common point of the circuit whose collector

5 чёрез резистор соединен с одной обкладкой дозирующего конденсатора накр:пител ,а его втора обкладка соедине на с змиттером транзистора линейного ключа,выполненного по схеме с общей 5 through a resistor is connected to one plate of the nakr: piter dosing capacitor, and its second plate is connected to the emitter of a linear switch transistor, made according to the scheme with a common

20 базой на транзисторе pi-n-p типа проводимости , и катодом диода,анод последнего и резистор базовой цепи упом нутого р-а-р транзистора соединеньс шиной питани , при этом к-общей 20 with a pi-n-p transistor type of conductivity, and a diode cathode, an anode of the latter and a base-circuit resistor of said p-a-r transistor connected to the power bus, with

Claims

25 points of connection of the collectors of the key transistor of the fadron and the transistor are connected to one side of the storage capacitor, and the other to the base of the current stabilizing transistor of the fadron. . The drawing shows the principal electrical delay scheme for 1) antastrone. The circuit consists of a three-transistor frondron 1 without the time of the master resistor and a capacitive drive without a cumulative encoder. Chro-irruptions Fadrone capacitor 1 is simultaneously accumulative for capacitive storage,. In the proposed device, the timing circuit consists of a storage capacitor 2, a linear switch on the transistor 3, a metering capacitor 4, a diode .5, a limiting resistor b, a normalizing transistor 7. Control pulses are fed to the accumulator at input 8, and fudron trigger pulses - at the entrance j9. The power supply is turned on between output 10 and the common point of the circuit. The fadron output pulse is recorded at pin C. The Phantron is made on a current-stabilizing transistor 12, a transistor 13, and a key transistor 14. The device operates as follows. In the initial state, the transistor 7 of the normalization of the cascade is open and is in saturation. The metering capacitor 4 is charged across the power supply circuit — diode 5 — resistor 6 — collector-emitter of transistor 7 — minus power supply bus. In this case, the transistor 3 of the linear key is open, since its voltage at the base is equal to the voltage at the emitter. Accumulative capacitor 2 is discharged Transistor 12 is closed. With the arrival of a negative pulse at the accumulator input 8, the transistor 7 closes, and the metering capacitor 4 starts discharging along the emitter-collector circuit of transistor 3 — the storage capacitor 2 — the current stabilizing transistor 13, transferring the charge to the capacitor 2. As soon as the potentials the capacitors are equalized, the transfer of charge from the metering capacitor 4 to the storage capacitor 2 stops and the transistor 3 closes. With the arrival of the next pulse, the process repeats. If the input 8 receives an impulse negative polarity, then a capacitor 2 will accumulate a voltage proportional to n. The triggering pulse arrives at the input 9 of the device, differentiates the input circuit, and then begins a relaxation process, and the duration of the pulse proportional to. the number of pulses n received at input 8 of the accumulator. Obviously, the starting pulse frequency at input 9 is much lower than the recording pulse frequency received at storage device input 8. The proposed device can be made in the form of a microchip on unpackaged transistors of types 2Т324, 2Т360 and: capacitors type К10-17В by hybrid thin-film Technology. Playing a little in accuracy, the proposed device can significantly simplify the us-. The quantized delay arrays, which, as a rule, are EXECUTED with the use of logical and counting circuits, in addition, it has low power consumption and can be used in small-sized telemetry communication equipment. Claim device A delay device containing a Fantastron, made on three transistors of an n-rtp type of conduction, characterized in that, in order to obtain a delay proportional to the number of pulses received at the control input of the device, the timing circuit is made in the form of a capacitive accumulator containing a transistor cascade connected by a circuit with a common emitter between the power supply bus and a common point of the circuit, the collector of which is connected through a resistor to one plate of the metering capacitor on the acopite l, and its second lining is connected to the emitter of a linear key transistor, arced according to a circuit with a common base on the pnp conductor type transistor, and the cathode of the diode, the anode of the latter and the resistor of the base circuit of the pnp transistor connected . With the power bus, one common plate of the storage capacitor is connected to the common point of the collectors of the fadron key transistor and the pnp transistor, and the fadron's current-stabilizing transistor base is connected to the other. Sources of information taken into account in the examination 1. USSR author's certificate number 506939, cl. H 03 K 5/13, 08/13/73.

2. Vazhenina Z.P. and others. Methods and schemes for the time delay of pulse signals. M., Soviet Radio, 1971, p. (prototype).