SU1160386A1 - Information input device - Google Patents

Abstract

A DEVICE FOR INPUTING INFORMATION containing a memory block, a comparison block, a timer, first and second registers, the first OR element, an indicating unit, a switch, an AND block, an encoder, a counter, a BAN element, a signal conditioner, a pulse generator, a second OR element , the block of switching elements, whose information outputs are connected directly to the information inputs of the signal conditioner, and through the encoder to one information input of the switch, the command outputs of the block of switching elements are connected to the inputs of the AND block, the control output — with the first control input of the timer, the outputs of the memory block are connected to one input of the comparison block, the others, input1.1 of which are connected to the outputs of the first register, which are outputs of the first group of the device, output the comparison unit is connected to the second control input of the timer, the reset input of which and the first reset inputs of the first and second registers are the first input of the device, the second - the reset inputs of the first and second registers are the second input of the device, the first output The timer is connected to the input of the AND block and the first input of the BAN, the outputs of the second register are the outputs of the second group of the device and are connected to the inputs of the first OR element whose output is the output of the device, the second timer output is connected to the control input of the switch and the control input the display unit, the output of the pulse generator is connected to the counting input of the counter, the outputs of which are connected to the information inputs of the display unit and other information inputs of the switch, the outputs of which are connected The information inputs of the first register are connected to the inputs of the second OR element, the output of which is connected to the second input of the BAN, the output of which is connected to the control input of the signal conditioner, the outputs of the AND block of the elements are connected to the information inputs of the second Register, characterized in that, in order to increase the reliability of the device by limiting the time about: selecting characters for the password, deo from 00 is entered in it, and the encoder, trigger and AND element, decrypted inputs pa connected to the outputs of the counter, the output to the installation input in “1 flip-flop, one installation input in“ About which is connected to one input of the AND element and the output of the signal conditioner, and the output to another input of the AND element, the output of which is connected to the synchronous input of the first register , the second timer output is connected to another input of the setting in “About the trigger.

Description

The invention relates to computing and is intended to enter information into a computer. A device for inputting information is known, comprising a memory unit, an indication unit, a comparison unit, a timer, two registers, two OR elements, an encoder, an AND element block, a delay element, and an information input keyboard. The device allows for differentiation of access to computer resources 1. The disadvantage of the device is low reliability, since it is possible to compromise the password during its typing on the keyboard due to visual reading by the intruder used when entering the password keys, which can lead to no authorized use of the device, and which leads to a high probability of selecting a password for a fixed time interval. The closest in technical essence to the invention is an information input device comprising a memory unit, a comparison unit, a timer, the first and second registers, the first OR element, the display unit, the switch, the AND block, the digitizer, the counter, the BAN element, the driver signals, pulse generator, the second element OR, a block of switching elements, the information outputs of which are connected to the information inputs of the signal conditioner, and through an encoder to one information input of the switch, the command outputs b The switching elements are connected to the inputs of the AND block, the control output is connected to the first control input of the timer, the output of the memory block is connected to one input of the comparison block, the other inputs of which are connected to the outputs of the first register, which are outputs of the first group of the device, output the comparison unit is connected to the second control input of the timer, the reset input of which and the first reset inputs of the first and second registers are the first input of the device, the second reset inputs of the first and second registers are the second In the device input, the first timer output is connected to the input of the AND block and the first input of the BANCH element, the second register outputs are the outputs of the second group of the device and are connected to the inputs of the first OR element, whose output is the device output, the second timer output is connected to the master the input of the switch and the control input of the display unit, the output of the pulse generator is connected to the counting input of the counter, the outputs of which are connected to the information inputs of the display unit and other information inputs of the comm the output of which is connected to the information inputs of the first register, the command outputs of the switching element block are connected to the inputs of the second OR element, the output of which is connected to the second input of the BAN element, the output of which is connected to the control input of the signal conditioner, the outputs of the And element block are connected to information the inputs of the second register 2. A disadvantage of the known device is the limited reliability. The aim of the invention is to increase the reliability of the device by limiting the time for selecting the characters of the password. This goal is achieved by the fact that the device for inputting information contains the memory block, the comparison block, the timer, the first and second registers, the first OR element, the display unit, the switch, the AND block, the encoder, the counter, the BAN element, the driver, pulse generator, the second element OR, the block of switching elements, the information outputs of which are connected directly to the information inputs of the signal conditioner, and through the cipher jop to one information inputs of the switch, the command outputs of the switching block The control elements are connected to the first control input of the timer block, the outputs of the memory block are connected to the oi.HKM inputs of the comparator, the other inputs of which are connected to the outputs of the first register, which are the outputs of the first group of the device. The output of the comparator unit is connected to the second control input of the timer, the reset input of which and the first reset inputs of the first and second registers are the first input of the device, the second reset inputs of the first and second regjjcTpoB are the second input of the device Actually, the first timer output is connected to the input of the AND block and the first input of the BANCH element, the second register outputs are the outputs of the second device group and connected to the inputs of the first element OR, whose output is the device output, the second timer output is connected to the control input switch the torus and the control input of the display unit, the output of the pulse generator is connected to the counting input of the counter, the outputs of which are connected to the information display unit and other information inputs of the switch, the outputs of which connected to information inputs of the first register, the command outputs of the switching element block are connected to the inputs of the second OR element, the output of which is connected to the second input of the BAN element, the output of which is connected to the control input of the signal conditioner, the outputs of the AND block of the elements are connected to the information inputs of the second register, the descramble, the trigger and the And element are entered, the inputs of the decoder are connected to the counter outputs, the output to the installation input in “1 trigger, one input of the installation“ About which is connected to one input th AND gate and the output of the signal, and an output - to another input of AND gate whose output is connected to the clock terminal of the first register, a second output delay section (timer) is connected to another input in the setting "On trigger.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - delay block circuit; in fig. 3 is a block diagram of a switch.

The device contains a memory block 1, a comparison block 2, a delay block 3, the first register 4, the second register 5, the first element OR 6, the indication block 7, the commutator 8, the block 9 And elements, the encoder 10, the counter 11, the BAN element 12, driver 13 signals, pulse generator 14, second element OR 15, switching element block 16, first element 17, trigger 18, decoder 19, first input 20, second input 21, first output group 22, second output group 23, output 24 frequency generator 25, the second element And 26, another counter 27, the third element And 28, the first group of elements And 29, the second group of elements And 30, the group of elements OR 31 and the element NOT 32.

The delay unit operates as follows.

By a signal at input 20, the counter 27 is set to a state in which the direct output of the counter 27 is a logical signal "1, and in the inverse state it is" O.

If present, the logical “O” signal at the inverse output of the counter 27 (at the direct output of the counter there is a logical “1) signal from the generator 25 does not arrive at the counting input of the counter 27. When a signal is received from comparison unit 2 and pressing the password key, the counter 27 is reset to "O", at the inverse output of which a "Resolution" signal is generated. (logical "1), which opens the element And 26. The counter counts the number of pulses generated by the generator 25 frequency. When the logical signal "1" is set at the direct output of the counter 27 (at the inverse output "O"), the flow of pulses to the counter input stops.

Thus, block 3 issues the “Repeat password” command at fixed intervals to block 7.

The first register, 4, is used to store typed passwords or to receive

information parts of the messages typed in block 16. It is a shift register.

The second register 5 is intended for receiving command parts of messages dialed at block 16.

The display unit 7 is designed to display the signal by which the operator needs to re-enter the password, as well as to display the sequence of decimal characters generated by the counter 11. It can be performed according to a circuit containing a decoder (for example, a chip to 514ID1) and a digital indicator ( for example, the ALS324A chip. Signaling the need to re-enter a password is provided by turning on a digital indicator.

The switch is designed to issue a code from the outputs of the encoder 10 or from the output DON of the counter 11 to the inputs of register 4, depending on the signal level from the output

block 3. The switch (Fig. 3) contains elements AND the first 29.1-29.4 and second 30.1 - 30.4 groups, elements OR 31.1-31.4 and the element NOT 32. When a logical signal "1 from block 3 from the outputs of the counter 11, the code through the elements AND 30.1-30.4 and the elements OR 31.1-31.4 is given to the inputs of register 4. When a logical signal is received, "About resolution is received

0 on elements AND 29.1-29.4 and the code from the outputs of the encoder 10 is fed to the inputs of register 4. Block 9 of the elements AND is designed to block the writing of commands to register 5 when the password expires. It may contain a group of elements And, the first

the inputs are connected to the outputs of block 16, and the second inputs are connected and connected to the output of block 3.

The encoder 10 is designed to convert the decimal number dialed

0 on block 16, in binary-tichny code.

Counter 11 is designed to form binary-decimal character sequences (0, 1, 2, 3, ..., 9) by counting pulses from generator 14. It is a binary-decimal counter.

5 The BAN 12 element is intended to prohibit (enable) the output of signals from the command switches of the block 16 to the driver 13 when the commands are typed (password).

Q Shaper 13 is designed to generate shear pulses. It may contain a delay element connected to the output of the OR element, the first inputs of which are connected to the information outputs of block 16, and the second input to the output

5 of the BANE element 12. The signal at the output of the imaging unit 13 must be set after the end of the transient process of the encoder 10, since the input of information in

the first register 4 is carried out on the leading edge of the shift signal.

The generator 14 is designed to generate pulses that ensure cyclic change of codes in the counter 11. The frequency of the generator 14 of pulses is selected from the condition of ensuring the reliability of visual reading of the required characters and their input by pressing the switches of the block 16. A suitable value of the frequency of the generator 14 can be 1 Hz.

The device works as follows.

When the power is turned on by the signal, the first and second registers 4 and 5 are reset by the tongue 20, and the first output of block 3 is set to the inhibit signal (logical "0) which keeps the elements AND block 9 in the closed state and allows the information to pass through the BANNER 12. At the second the output of block 3 establishes a signal (logical "1), including the display unit 7 and allowing the passage of information through the switch 8 from the output of counter 11 and prohibiting the passage of information from the exit of the equalizer 10, as well as allowing the installation of a trigger ra 18 in "On the signals output from block 13.

To unlock the device, the operator generates a password.

The counter 11 counts the pulses from the generator 14, in which the cyclic Sequence of characters (0,1,2, 3, ..., 8,9,0,1, ...) is formed, displayed on the display unit 7. At the same time, information from the output of the counter 11 goes through the switch 8 to the 4 user register at the moment of indication on the unit 7 of the required characters presses information or command switches, which also serve to enter the password.

When any information switch of the block 16 is pressed, the output of the imager 13 generates a signal coming through the open element 17, on the leading edge of which the next character from the switch output is written to the register 4. The next character from the output of the switch 8 to the register 4 can also occur any command switch signal, which comes from the output of the command switches of the block 16 through the element OR 15, the open element BAN 12, the imaging unit 13 and the element And 17.

After writing the next character in the register

4, a logical "O" is set at the falling edge of the signal from the driver 13 at the output of the trigger 18, which prohibits the passage of signals from the driver 13 through the element 17 and the input of the register 4. When code 11 "appears at the output 11 of the decoder 19, a pulse is generated by which output

trigger 18 sets a logical "1" signal, which ensures further input of characters into register 4.

When comparing the dialed code with the reference stored in memory block 1, the comparison block 2 provides a resolution signal to block 3.

After pressing the password entry switch, block 3 issues an enable signal to block 9 of the elements And, which provides input of commands from block 16 to register 5 and prohibits the passage of information through the element BAN 12.

At the same time, the second output of block 3 establishes a signal (logical " O), by which the display unit 7 is quenched, the information from the output of the tamper 10 through the switch 8 to the input of the register 4 and the information from the output of the counter 11 is prohibited through the switch 8 to the input of the register 4 as well as the installation of the trigger 18 in the "O on signals from Exodus of the imaging unit 13 (the logical" O), i.e. after entering the next character in register 4, blocking of inputs of subsequent characters is not performed for some time.

Block 3 begins to form a time interval during which commands and information can be entered into the computer via outputs 23 and 22.

After that, the operator can type the information and command parts of the messages at block 16. Moreover, after typing the command, output 24 generates a "Readiness" signal, according to which the computer receives the message at outputs 22 and 23.

After receiving the message, the computer reset registers 4 and 5 at input 21. After a fixed time interval has elapsed, unit 3 closes AND elements of unit 9 (thus blocking the input of commands) and turns on display unit 7, and it is possible to enter the password in the same way as described. In this case, the operator must re-enter the password.

Thus, the protection against unauthorized access is enhanced.

In the known device, when used in a password, characters are arranged in ascending order, they are set in one cycle of recalculation (0,1,2,3, .., 9) of a counter intended to form characters (for example, password 245 can be typed for one recalculation counting cycle).

In the proposed device, by introducing a trigger, an AND element and a decimator, the input of characters of the password is possible only in various cycles of the counter recalculation, since after the next character is entered, the next-time characters are blocked until the start of the next cycle. For example, a three-bit password 245 may not be dialed

in less than three cycles. Therefore, it will take more time for the password to be picked by the intruder, which leads to an increase in the reliability of the guard against unauthorized access.

In a known device, different passwords can be dialed for different numbers of cycles (for example, password 245 can be dialed in one cycle, and password 542 in three cycles). Therefore, users more often set passwords that can be typed in the minimum number of cycles, in particular, in one cycle. Taking this into account, the intruder first of all gathers passwords, which can be entered in one cycle, found in two cycles, etc., which leads to quick selection of passwords. In the proposed device, any password is accumulated per number of cycles equal to the password depth. For example, passwords 245 and 542 can be typed in three cycles. Therefore, users can set any code values as passwords with equal probability, which increases the time for the intruder to select a password.

FIG. 2

Claims (1)

INFORMATION INPUT DEVICE, comprising a memory unit, a comparison unit, a timer, first and second registers, a first OR element, an indication unit, a switch, an AND element block, an encryptor, a counter, a PROHIBIT element, a signal conditioner, a pulse generator, a second OR element, a block switching elements, the information outputs of which are connected directly to the information inputs of the signal conditioner, and through the encoder to one information inputs of the switch, the command outputs of the block of switching elements are connected to the inputs block of elements AND, the control output is with the first control input of the timer, the outputs of the memory block are connected to one of the inputs of the comparison block, the other inputs of which are connected to the outputs of the first register, which are the outputs of the first group of the device, the output of the comparison block is connected to the second control input of the timer, the reset input of which and the first reset inputs of the first and second registers are the first input of the device, the second - the reset inputs of the first and second registers are the second input of the device, the first output of the timer is connected n with the input of the AND block and the first input of the BAN element, the outputs of the second register are the outputs of the second group of the device and are connected to the inputs of the first OR element, the output of which is the output of the device, the second timer output is connected to the control input of the switch and the control input of the display unit, generator output pulses connected to the counting input of the counter, the outputs of which are connected to the information inputs of the display unit and other information inputs of the switch, the outputs of which are connected to the information the inputs of the first register, the command outputs of the block of switching elements are connected to the inputs of the second OR element, the output of which is connected to the second input of the FORBID element, the output of which is connected to the control input of the signal conditioner, the outputs of the block of elements AND are connected to the information inputs of the second register, characterized in that, in order to increase the reliability of the device by limiting the time for selecting the password characters, a decoder, a trigger, and an element And are introduced into it, the inputs of the decoder are connected to the outputs of the counter, the output is to the installation input in “1” of the trigger, one installation input in “0” of which is connected to one input of the And element and the output of the signal conditioner, and the output to the other input of the And element, the output of which is connected to the clock input of the first register, the second timer output is connected to the other input to the “0” trigger. SU .. „1160386>