SU1149214A1 - Controlled filter - Google Patents

Abstract

A CONTROLLED FILTER containing the first low-pass filter, the first and second comparison blocks, the first adder, the first analysis block, which includes the third comparison block. The first sign detector, the first delay unit and the first multiplication unit, the second input of which is connected to the output of the first sign detector, the second delayed unit, the fourth comparison unit, the second sign detector, the third delay unit and the second multiplication unit, the second input connected to the output of the second sign detector, a series-connected inverter and a second adder, a series-connected fifth comparator unit and an integrator, the output of which is connected to the first input p The first comparison unit, the first input of the analysis unit is connected to the input of the second delay unit, the second input of the fourth comparison unit and the output of the first low-frequency filter, characterized in that, in order to improve the accuracy of the useful signal extraction by the filter, a second low-frequency filter is introduced into it a block, a successively connected third (L low frequency filter, a third adder, a third multiplication unit and a fourth adder, a successively included second analysis unit, a fifth adder, a first division unit and a quarter the third multiplication unit, the third analysis unit and the second division unit, the third division unit and the fifth multiplication unit, in series, the input of the first low-pass filter are connected to the input of the controlled filter, the first input of the first comparison unit and the second inputs of the first, second and second The third analysis block, the output of the first low-pass filter is connected to the second input of the fourth multiplication unit, the first input of the first adder, and through the first comparison block with the input of the second low filter often s and the first input of the second comparator block, the second filter output low

Description

the frequency is connected to the second input of the first capacitor and through the second comparison unit to the input of the third low-frequency filter, the output of the first mat is connected to the first. the input of the second analysis unit and the second inputs of the third adder and the fifth multiplication unit, the output of the third adder are connected to the second input of the fifth adder through the third analysis unit, the third input of which is connected to the output of the first analysis unit and the second input of the first division unit , the output of the second analysis unit is connected to the first input of the third division unit, the output of the fifth adder is connected to the third input of the third division unit and through the second division unit to the second input of the third multiplication unit.

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The second and third inputs of the fourth adder are connected to the outputs of the fifth and fourth multiplication units, the output of the fourth module's slots is pre-assembled to the output of the controlled filter, the second input of the analysis units is connected to the first input of the third comparison unit, the second input of which is connected to the first input of the analysis units and the output is connected to the input of the first sign detector, the output of the first multiplication unit is connected to the input of the inverter, and the output of the second adder is connected to the second input of the fifth comparison unit, the output of the second multiplication unit is connected to eye input of the second adder, the integrator output is connected through a non-linear unit to the output of the analysis unit.

The invention relates to automation, namely filtering interference, and can be used to isolate the non-stationary useful low-frequency component of the measured signals against the background of relatively high-frequency interference with complex static properties and the presence of occasional coarse emissions.

Known vernial tracking systems, for example, containing the first and second low-pass filters, the first, second and third comparison units, the third low-frequency filter and the adder, the second and third input of which is connected to the outputs of the first and second low-frequency filters, respectively, are connected in series, The low frequency filter outputs are also connected to the second inputs of the respective comparison units. -Vo. The input value is reproduced by the method of successive approximations Pj,

The lack of noisy tracking systems when using them as a smoothing filter is low accuracy in extracting the useful signal due to the fact that the non-stationary properties of the useful signal and interference are not taken into account.

Closest to the invention to the technical essence is a smoothing filter comprising a low-pass filter comprising a first comparator unit connected in series, a limiter and a first integrator, the output of which is connected to

the first input of the first unit of comparison, the analysis unit, which includes the first scaling unit, the first and the second control devices, sequentially connected to the second scaling

unit and first inverter, serially connected first sign detector, first delay unit, first multiplication unit, second comparison unit, second integrator, third unit

comparison, the third scaling unit, the second inverter and the first adder, the second delay unit connected in series, the fourth comparison unit, the second sign detector, the third delay unit, the second

block of multiplication, five blocks compared to ni, third integrator, sixth block

compare, fourth scaling

block and second adder, and you3

the moves of the first and second setters are connected to the second inputs of the third and sixth comparison blocks respectively, the outputs of the second and third integrators are connected to the second inputs of the second and fifth comparison blocks respectively, the outputs of the first and second sign detectors are connected to the second inputs of the first and second blocks respectively multiplying, the output of the third unit of comparison is connected via the first scaling unit to the second input of the second adder, the output of which is connected to the auxiliary input of the limiter, the output of the sixth the comparison unit is connected to the input of the second scaling unit, the output of the first inverter is connected via

the first adder to the auxiliary input of the first integrator, the output of the first comparison unit is connected to the input of the first sign detector, the output of the first integrator to the input of the second delay unit, the second input

-four comparison unit and the output of a smoothing filter, the input of which is connected to the second input of the first comparison unit.

In the smoothing filter, the input signal is fed to the first comparison unit, where the output signal of the first integrator about the smoothed value of the input signal is subtracted from it. The difference signal is limited by a limiter and fed to the input of the first integrator. The remaining blocks of the smoothing filter are designed to adapt the restrictor restriction zone and the constant integration time of the first integrator. Adaptation is performed in two ways: by the deviation of the recorded signal from its smoothed value and by the rate of change of the estimate of the useful (smoothed) signal. For the first and second indicators, the analogs of the sign-based autocorrelation moments are determined, their deviations from the desired values are estimated, and the corrections of the restriction zone and the constant integration are calculated in proportion to these deviations 2j.

The disadvantage of the smoothing filter is the low accuracy of the useful signal due to

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relatively slow adaptation of the smoothing filter parameters.

The purpose of the invention is to improve the accuracy of the useful signal. 5 The goal is achieved by the fact that in the controlled filter containing the first low frequency filter, the first and second comparison blocks, the first adder, the first block

0 analysis, including a third unit of comparison, serially connected to the first sign detector; per. the left delay unit and the first multiplication unit, the second input of which

5 is connected to the output of the first sign detector, a second delay unit connected in series, a fourth comparison unit, a second sign detector, a third delay unit

Q and the second multiplication unit, the second input of which is connected to the output of the second sign detector, a series-connected inverter and a second adder, are sequentially

5 included fifth comparison unit and integrator, the output of which is connected to the first input of the fifth comparison unit, the first input of the analysis unit is connected to the input of the second unit

Q delay, the second input of the fourth comparison unit and the output of the first low-pass filter, the second low-pass filter, the nonlinear block, the third low-pass filter, the third adder, the third multiplication unit and the fourth adder, the second analysis block, the fifth adder , the first division unit and the fourth survival unit, the third analysis unit in series and the second division unit, the third division unit in series and the fifth multiplication unit, in series, the control input the inlet filter is connected to the input of the first low frequency filter, the first input of the first comparison unit and the second inputs of the first,

the second and third analysis units, the output of the first low-pass filter is connected to the second input of the fourth multiplication unit, the first input of the first adder and through the first

Comparison unit with the input of the second

the low frequency filter and the first input of the second comparison unit, the output of the second low frequency filter is connected to the second input of the first adder via the second compare-1PC unit to the input of the third low-pass filter, the output of the first adder is connected to the first input of the second analysis unit and to the second inputs of the third adder and the fifth unit, the output of the third adder, through the third analysis unit, is connected to the second input of the fifth source, the third input of which is connected to the output of the first analysis unit and the second input of the first unit When the output of the second analysis unit is connected to the first input of the third delegate unit, the output of the fifth adder is connected to the second input of the third division unit and via the second. a dividing dividing unit with a second input of the third multiplication unit, the second and third inputs of the fourth sum of the controller are connected to the outputs of the corresponding fifth and fourth multiplication blocks, the output of the fourth adder is connected to the output of the controlled filter, the second input of the analysis units is connected to the first input of the third comparison unit the second input of which is connected to the first input of the analysis units, and the output to the input of the first sign detector, the output of the first multiplier is connected to the input of the inverter, and the output of the second adder to the second input of the fifth block The output of the second multiplication unit is not connected to the second input of the second sum, the integrator output is connected to a single nonlinear cut to the output of the analysis block. Fig. 1 shows a block diagram of the controlled filter, where x (t) is the input signal of the controlled filter, x (t) is the output (useful, smoothed) signal; Fig.2 is a block diagram of analysis units. The controlled filter contains the first low-frequency filter 1, which includes a series-connected comparison unit, a limiter in the form of an amplifier with saturation, and an integrator whose code is connected to the input of the comparison unit, the first comparison unit 2, the second low-frequency filter 3, having the same structure, as the first low-frequency filter 1, the second block 4 of the comparison, the third low-frequency filter 5 having the same structure. 46 as the previous two filters, the first 6 and third 7 adders, the third 8, the fifth 9 and the fourth 10 multiplication blocks, the fourth adder 11, the first 12, the second 13 and the third 14 blocks analyzed the fifth adder 15, the second 16, the third 17 and the first 18 division units, the third comparison unit 19, the first 20-character detector, the first delay unit 21, the first multiplication unit 22, the inverter 23, the second delay unit 24, the fourth comparison unit 25, the second sign detector 26, the third delay unit 27 , the second multiplying unit 28, the second adder 29, the fifth comparing unit 30, the integrator 31 and the nonlinear block 32, real izuyuschy piecewise linear relationship. The control filter operates as follows. The filter input signal x (t) is fed to a first low frequency filter T, in which the low frequency component of the signal (t) is extracted. The signal x (t) is subtracted in the first comparison unit 2 from the signal x (t) coming from the input of the controllable filter. The signal of the received difference (t) x (t) - x4t) is fed to the second low-pass filter 3. The settings of the second low-pass filter 3 are chosen in such a way - so that its inertia is 1.5–2 times less than that of the first low pass filter 1. The output of the second low-pass filter 3 Dx (t) is algebraically summed in the first adder 6 with the output of the first low-pass filter 1. The output of the first adder 6 receives a signal + ux (t) x (t) of the input signal smoothed at the second level). The signal x (t) contains higher frequency components than the signal x (t) from the first level. Similarly, a smooth XCI signal X is obtained (t; at the third level. For this, the output signal of the second low-pass filter 3 is subtracted in the second comparison block 4 from the output signal of the first comparative block 2. The received different signal (t) is smoothed in the third low filter 5 frequencies, the inertia of which is 1.5–2 times less than the inertia of the second low frequency filter 3, and is algebraically in the third adder 7 with the output signal of the first adder 6. The output signal x (t) of the third adder 7 lW / .X (t) X (t) + u to (t) where ux (t) is the output the signal of the third low-frequency filter 5 contains more high-frequency components than the signal x (t). The smoothed signals x (t), x (t) and) are multiplied from three levels, respectively, in the fourth 10, the fifth 9 and the third 8 blocks multiplying the signals of adaptable weights k4t), k (t) and and algebraically summed in the fourth matrix 3, the output of which is the if signal (ti-kHii Htbk (iix (. The weights k are adapted depending on the properties of the input deviations) signal x (t) from its smoothed values at each level and from properties Amichai smoothed signal; To this end, the input signal x (t) and the signals x4t), x (t),) go to the first 12, second 13 and third 14 blocks of analysis, which have the same structure (Fig 2). The indicator characterizing the deviation properties x {t) from x (t) where M I, II, III is determined, for example, in the first analysis block 12 by the expression (ibx4ti -6i n x a-S) -xHt-t; where o is the delay time interval chosen in each specific case during the practical adjustment of the filter. The index f has the following properties: if there is a systematic deviation of x (t) from x (t) of a positive or negative value, then f (tj tends to +1, if there is no systematic deviation, then f "(t) tends to -1 The desired value of the indicator f, (t) is -1. For realizing and expressing (5) in the third comparing unit 19, the signal x (t) subtracted from the signal x (t) from the second input of the first analysis block 12 is subtracted from the first input of the analysis block 12. The signal of the difference obtained is processed in the first detector of the 20 sign with the law ohm operation. e „,. (. i., p.„ „{: g, /:;: / where 6out (t) and EBh (t) respectively the output and input signals of the sign detector. C c) 1 input of the first detector A 20 digit signal is fed to the first multiplication unit 22, where it is multiplied by its own value, which is delayed in the first delay unit 21 by the time interval 2. The indicator characterizing the properties of the useful signal, namely, its smoothness, is determined, for example, in the first analysis unit 12 in the expression e2 (t) (f) -x4i-t -si n xHt ob) c (-2J). Indicator S (t), like f, (t), tends to either +1 or -1. However, the desired value of S (t) is +1, i.e. it is required that the signal be smooth, and hence its increments on neighboring stations are of the same sign. The day of implementation of the php (7) signal is about x (t). from the first input of the analysis unit 12 is delayed in the second block 24 of the delay for the time interval. Then the output sig. The second delay unit 24 is subtracted in the fourth comparison unit 25 from the signal x (t). The output signal of the fourth comparison unit 25 is processed using a second detector 26 of the sign, the third delay unit 27, and the second multiplication unit as well as the output of the third block 19 comparison. . The indicators fi (t) and g, (t) are algebraically coded with. Preliminary, the signal about ((t) is inverted by the inverter 23. This is because the indicators f, (t) and f, (t) have different desired values. The output of the inverter 23 is fed to the input of the second adder 29j where it is combined with the output of the second multiplication unit 28. The received signal from the output of the second sum of the torus 29 is fed to the five comparison unit 30, in which the output signal of the integrator 31 is subtracted, and the resulting difference $ adet to the input of the integrator 31, the output of which receives with the signal about the smoothed value (t) of the sum of the exponents f, (t) and {, t}. This signal arrives at the nonlinear block 32, in which the piecewise-mechanic dependence is realized, approximating a exponential function, for example, of the form A () where A - a positive number. At the output of the nonlinear block 32 a signal is obtained, which always has a positive value. The weight coefficient k (t) is calculated by the expression)) where :- (t),) and) are the output signals of the first 12, second 13 and the third 14 analysis units. For this, the output signals of the analysis block are summed in the fifth adder 15, the signal from the output of which has an effect of about 150 thousand rubles. in year

is given to the input of the first block 18 due to a decrease in the specific stratification in which the coke operating stage is produced by 0.3-0.5% and an increase in the division of the output signal E (t) or the furnace output by

the first block 12 analysis on the output of 0.6-0.8%. Signal signal of the fifth adder 15. The decoder signal of the first division unit 18 about the value of k (t) is fed to the second input of the fourth multiplication unit 10. Weighting coefficients k (t) and) j are determined in the same way for which the third 17 and second 16 division blocks are used. In the described controllable filter, three levels of smoothing are given. By analogy, a control filter can be constructed with a large number of levels. The introduction of several smoothing levels with different dynamic properties into a controlled filter makes it possible to more quickly track fast changes in the useful signal, for example, of a pulse-like type, which improves its accuracy. From the simulation results, it follows that the standard deviation of the estimate of the useful signal from its actual 1 value for the proposed controlled filter is 8–12% less than for the known filter. Use- The establishment of a controlled filter in predictive control systems leads to an increase in control accuracy by 0.5-1%. This, in turn, gives, for example, when regulating the heat and slag regime of a blast furnace, economic

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Claims (1)

CONTROLLED FILTER containing the first low-pass filter, the first and second comparison units, the first adder, the first analysis unit, including the third comparison unit, connected in series with the first sign detector, the first delay unit and the first multiplication unit, the second input of which is connected to the output of the first sign detector connected in series to a second delay unit, a fourth comparison unit, a second sign detector, a third delay unit and a second multiplication unit, the second input of which is connected to the output of the second sign detector, last the inverter and the second adder, the fifth comparison unit and the integrator connected in series, the output of which is connected to the first input of the fifth comparison unit, the first input of the analysis unit is connected to the input of the second delay unit, the second input of the fourth comparison unit and the output of the first low-pass filter, characterized in that, in order to improve the accuracy of the selection of the useful signal by the filter, a second low-pass filter, a non-linear block, 3 series-connected third low-pass filters, are introduced into it, t the first adder, the third multiplication unit and the fourth adder, the second analysis unit, the fifth adder, the first division unit and the fourth multiplication unit, the third analysis unit and the second division unit, the third division unit and the fifth multiplication unit in series, the input of the first a low-pass filter is connected to the input of the managed filter, the first input of the first comparison unit and the second inputs of the first * second and third blocks / analysis, the output of the first low-pass filter is connected to the second input of the fourth multiplication unit, the first input of the first adder and through the first unit of comparison with the input of the second low-pass filter and the first input of the second comparison unit, the output of the second low filter SAL · "1) 1149214 1 149214 frequency is connected to the second input of the first adder and through the second block of comparison to the input of the third low-pass filter, the output of the first adder is connected to the first. the input of the second analysis unit and to the second inputs of the third adder and the fifth multiplication unit, / the output of the third adder through the third analysis unit is connected to the second input of the fifth adder, the third input of which is connected to the output of the first analysis unit and the second input of the first division unit, the output of the second analysis unit connected to the first input of the third division block, the output of the fifth adder is connected to the second input of the third division block and through the second. The division block with the second input of the third multiplication block, the second and third inputs of the fourth sum Ora are connected to the outputs of the fifth and fourth multiplication blocks, the output of the fourth adder is connected to the output of the controlled filter, the second input of the analysis blocks is connected to the first input of the third comparison block, the second input of which is connected to the first input of the analysis blocks, and the output to the input of the first detector sign, the output of the first multiplication unit is connected to the input of the inverter, and the output of the second adder is connected to the second input of the fifth comparison unit, the output of the second multiplication unit is connected to the second input of the second adder, the output is integ The radiator is connected via a non-linear block to the output of the analysis block.