SU1143702A1 - Glass for integrated ciruits - Google Patents

Abstract

GLASS FOR INTEGRATED SCHEMES, including SiO,, BaO, SrO, ZrOg, characterized in that, in order to obtain a consistent silicon-silicon spa, it contains these components in the following ratio, wt%: SiO 60-74 AijO, 8-t6 4 -26 BAO 2-18 SrO 0.5-4 2 gOg + SrO is 12-28%. and EBAO

Description

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WITH

About the Invention The invention relates to the composition of non-crystallizing glasses designed for intercomponent, interlayer insulation, passivation, and the encapsulated protection of silicon || 1x integrated circuits (ICs). The following requirements are imposed on glass designed for intercomponent dielectric silicon silicon ICs: high dielectric characteristics (i 10, tgS i 30:10, / RU 10 Ohm.cm), CTLR consistency with my silicon roe (1b - To resistance to heat treatments, applied in the planar technology of manufacturing IC (t.), The absence of elements doped with silicon (B, P, Sb, As, etc.) and alkali metals (Na, etc.), high chemical resistance (1 hydrolytic class.) Solder glass is known for junctions with molybdenum, including, sec.%: SiOg 55-6 8; 15-18; CaO 7-13; BaO 6-16j with a weight ratio of AIjOd / CaO + BaOot 0.6: 1 to 1: 1 1. The disadvantages of this glass are relatively high CTE (42-48 "ld K) that does not allow to obtain consistent junctions with a crère, as well as a relatively low temperature of the onset of deformation (.725 ° C). The closest to the invention of the technical essence and the achieved result is glass 2J, from which dielectric layers are made for interlayer insulation in the manufacture of enclosures integrated circuits, as well as for obtaining junctions by refractory metals, including May.% : SiO 45-55 A disadvantage of the known glass is the high CTE (45-65) 00, which does not allow its use of hdp to produce consistent silicon junctions. The aim of the invention is to obtain a coordinated silicon pool. The goal is achieved by the fact that glass for integrated circuits, including SiOj,, BaO, SrO, ZrO, contains these components in the following ratio, wt.%: 5, BaO +. SrO is 1 2-28%. As source components. use SiOj,, BaCOj, SrCOg and ZrOj of the OFS brands. The original components are weighed in accordance with a given composition and thoroughly mixed in a shmovaya mortar. The glasses were synthesized in an induction furnace in a platinum-rhodium crucible at 1700 ° C with a holding time of 10 hours after the charge was melted. The production of glasses is carried out in the form of a granulate by casting molten glass melt into distilled water. To measure CTLR and t. cast samples in the form of rods (50x5x5 mm) .; The glass granulate is ground in a shma drum on a planetary mill to a specific surface of 5000. The formation of vitreous layers on silicon wafers is carried out using the HF method of magnetron sputtering. When spraying, a powder glass target is used, the formation of which is realized by uniformly applying glass powder to a metal cathode (diameter 130 mm). The thickness of the glass layer is 4 mm. The formation of vitreous films is carried out in the following mode: the RF generator current is 0.35 A, the target voltage is 200 V, the bias voltage on the substrate is (-50) V, the total pressure of the working gas is 0, 1 Pa, the composition working gas - 90% Ar, 10% 02. The deposition rate of films in this mode is about 20 nm / min, the temperature of the substrates does not exceed. Get films with thicknesses of 0.5; one; 5 and 10 microns. As the substrates, microcrystalline silicon plates of the grades KDB-10 and KES-0.01 are used. 60 mm. in tab. 1 shows the composition of the glass. The values of CTLR, t., Glasses, dielectric characteristics of vitreous films, as well as the values of the boom on the silicon wafer plates with vitreous films, are given in Table. 2. As follows from the table. The 2 values of KtJIP glasses are close to the CTLR of monocrystalline silicon (in the range of 2–5 500 s), which provides almost zero values of the deflection of the silicon wafers with a vitreous film (2 µm). The proximity of the CTLR of silicon and glass provides a consistent, unstressed spa, which reduces the dislocation density in silicon and improves its electrophysical parameters. Stack films based on the proposed compositions have high dielectric characteristics. Due to the fact that t, the glasses of the proposed compositions are superior, the silicon structures with glassy films allow long thermal operations. Table 1 24 csi used in the planar technology of producing ICs (diffusion, annealing, oxidation). After heat treatment of silicon plates with glassy films of compositions 1-5 at 600-1200 0 for 2 hours, no changes in the dielectric characteristics and deflection boom values are observed. Differential thermal analysis of glasses showed that they are resistant to crystallization. Studies conducted by X-ray, G-spectroscopic and electron microscopic analyzes have shown that both the original films and the films heat-treated in the temperature range of 600-1200 s are amorphous. Depending on the specific application in silicon IC technology, glass can be used both in the form of vitreous films, obtained by RF-ion-plasma, RF-magnetron sputtering, centrifugation, and in the form of monolithic glass substrates.

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16 10 12

4 5

14

1.5

0.5

9

2

4 1

18

eight

Hsh resistance (hydrolytic. Class)

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tgS at f, t 20 ° С, X 10-

RU at t 200 ° C,,

table 2

10.0

8.5

10.0

9.0

17

20

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Claims (1)

GLASS FOR INTEGRAL CIRCUITS, including SiO ^, Αί _? Ο ₅ , BaO, SrO, Zr0 ₅ , characterized in that, in order to obtain a consistent junction with silicon, it contains these components in the following ratio, wt.%: SiO ₂ 60-74 AR ₂ O ₅ 8-1.6 BaO4-26 SrO2-18 Zr0 ₂ 0.5-4; moreover, ^ BaO + SrO is 12-28%. 1 1143702 The aim of the invention is semi-