SU1140249A1 - Stage of digital store - Google Patents

Abstract

CASCADE DIGITAL DRIVE, containing a register and a binary adder, the first. the input of the lower bit is connected to the lower code bus, the transfer input is connected to the input transfer bus, the transfer output is connected to the output transfer bus, and the second inputs of the binary adder are connected to the outputs of the corresponding register bits, the clock input of which is connected to the bus pulse clock, which differs by the fact that, in order to increase speed, a coding block and a switch are entered into it, and an additional bit is entered into the register, the output of which is connected to the control of the switch input and to the synchronous transfer bus when it first inputs bits are connected to the switch sootvetstvuyuschm kodrvm older tires and inputs a coding unit, the second input - to the corresponding outputs of the encoding unit, and the switch outputs are connected to. the first inputs of the corresponding high bits of the binary adder, the outputs of the sum and transfer of which are connected to the information inputs of the corresponding register bits.

Description

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ISii. The invention relates to a pulse technique and can be used in digital frequency synthesizers. Known digital drive containing a parallel register, a multiplexer and two adders, the first input of the first of which is connected to the input bus, the clock input of the parallel register is connected to the pshnoy clock pulses, and its output - to the second input of the first adder, the output of which is connected to the first inputs of the second an adder and a multiplexer, the second input of which is connected to the transfer output of the first adder and the third one - to the output of the second adder, the second input of which is connected to the auxiliary input bus, the output multiplex The ora is connected to the input of the parallel register lj. However, this device has limited speed and sufficient complexity (contains two adders). The closest in technical essence to the present invention is a cascade of a digital storage device containing a parallel register, the first and second binary adders, the first inputs of the first binary adder connected to the code buses, and the second inputs connected to the outputs of the corresponding parallel register bits, the clock input of which is connected with the clock bus, the information inputs of the parallel register are connected to the sum outputs of the second binary adder, the inputs of which are connected to the sum outputs and transfer the first binary adder 2. The disadvantage of such a cascade of a digital accumulator is the low speed determined by the sum of the switching delay of the parallel register and the delay of the signal passing through two serially connected binary adders. In addition, the cascade has the functionality because it does not allow; to implement the function of a binary digital storage device. The purpose of the invention is to increase the speed of the digital cascade by a storage device. The goal is achieved by the fact that a cascade of a digital storage device containing a register and a binary adder, the first input of the lower junior code of which is connected to the first bus, the transfer input is connected to the input transfer bus, the transfer output is connected to the output transfer bus, and the second inputs of the binary adder are connected To the outputs of the corresponding register bits, the clock input of which is connected to the clock bus, a coding block and a switch are entered, and a register is added to the register and the output of which is connected to the control input comm the first inputs of the switch bits are connected to the corresponding higher code bus and coding block inputs, the second inputs are connected to the corresponding outputs of the coding block, and the switch outputs are connected to the first inputs of the corresponding high bits of the binary adder, the sum outputs and the transfer of which is connected to the information inputs of the corresponding register bits. The drawing shows a structural electrical circuit of a cascade of a digital storage device. The digital storage cascade contains a binary adder 1 (parallel with sequential transfer), register 2, (parallel), 3 clock bus, input and output 5 transfer buses, low code bus 6, high-speed code pins 7–9, bus 10 synchronous transfer, switch 11, block 12, coding, bus 13, selection module recalculation of the cascade of the digital storage device. Block 12 contains .inverter 14, element 15 exclusive OR-NOT and element 16 OR. In the device, the clock input of the register 2 is connected to the bus 3, the transfer input of the lower bit of the binary adder 1 is connected to bus 4, the transfer output of the higher bit of the binary adder 1 is connected to bus 5 and the information input of the additional bit of register 2, the first input of the lower digit Yes, the binary adder 1 is connected to the bus 6, and the first inputs of the higher bits of the binary adder are connected to the corresponding outputs of the switch 11, the control input of the switch 11 is connected to the terminal 10 and to the output of the additional register bit 2, the output The remaining bits of which are connected to the second inputs of the corresponding bits of binary adder 1, the first inputs of switch 11 are connected to buses 7–9 and to the outputs of block 12, the second inputs of switch 11 are connected to the codes of block 12, an additional control input of the switch is connected to the bus 13. The cascade of the digital drive works as follows. Clock pulses are sent to the device bus 3, the output signal is removed from bus 5 or from bus 10 devices. When a potential signal with a logic level of zero is applied to bus 13, regardless of the presence or absence of a synchronous transfer signal, the first inputs. As a result, from the code buses 6-9, the input information in the binary code, without a change, goes directly and through the switch 11 to the first inputs of the binary adder 1, and the device realizes the function of the binary digital storage device. When a potential signal with a logic unit level is applied to bus 13, switch 11 begins to respond to a synchronous transfer signal arriving at its control input. The device works as follows. Input information in the binary-decimal code 1-2-4-8, corresponding to the values of numbers from O to 9, goes to the code bus 6-9. In block 12, the transcoding operation is equivalent to adding a fixed number 6 to the input information. In the absence of a synchronous transfer signal, the input information from the coding buses 6–9 goes directly without any changes, as well as through the first inputs and outputs of the switch 11 to the first inputs of the binary adder 1. When a synchronous transfer signal occurs, the outputs of the switch 11 transfer information from its second inputs. In this case, the first inputs of the binary adder 1 receive information in a binary-decimal code with an excess of 6, corresponding to the numbers 494 from 6 to 15. As a result, the device implements the function of the decimal drive. When the device is implemented on the same type of logical elements, the switching time of the switch does not exceed the time of forming the transfer signal of the first low-order bit of the binary adder. In this case, the switching of the codes at the first inputs of the second and subsequent higher bits of the binary adder does not affect the generation time of the output signals of the parallel binary adder with sequential transfer. As a result, the speed of the digital storage cascade with a recalculation module equal to 10 is the same as with the recalculation module equal to 16, i.e. determined by the sum of the switching delay of the parallel register and the delay of the signals passing through the binary adder. A multi-stage parallel digital storage device with synchronous group transfer can be built on the basis of the device. For this, the 4 transfer bus of each subsequent upper stage must be connected to the bus 10 of the synchronous transfer of the previous stage, and the tires of 3 all stages are combined. The peculiarity of such a drive is that the maximum clock frequency of the device is determined by the speed of one stage and does not decrease with increasing number of stages. Digital storage with synchronous transfer can be used in systems that do not have special requirements for the amount of delay in the formation of a signal of synchronous transfer, for example, in decade pseudo-regular pulse train generators — in systems of direct frequency synthesis, as well as as a fractional bits block. Dov splitter, frequencies with fractional variable division factor - in systems of indirect frequency synthesis. The speed of the device being predicted is one and a half times higher than that of the prototype. This is about s-. This is because the speed of the base object is determined by the sum of the delays in passing the signal through three approximately equal in speed $ 1140,249b

functional unit - a parallel. The invention has a wide functional register and two binary sum capabilities, since

mator. The performance offered by the cascade of the digital cascade of the digital accumulator of the determinant can be realized with a rather simple pedal with the yumma of the switch-through path 5

signals only through one binary function decimal and function

adders parallel register.binary storage.

Claims (1)

A DIGITAL STORAGE CASCADE containing a register and a binary adder, the first input of the least significant bit of which is connected to the lower code bus, the transfer input to the input transfer bus, the transfer output to the output transfer bus, and the second inputs of the binary adder connected to the outputs of the corresponding register bits the clock input of which is connected to the clock bus, characterized in that, in order to improve performance, a coding unit and a switch are inserted into it, and an additional bit is connected to the register, the output of which is connected the control input of the switch and the synchronous transfer bus, the first discharge switch inputs connected to respective word lines and older coding unit inputs, the second input - to the corresponding outputs of a coding unit, and outputs a switch coupled 's. the first 5 inputs of the corresponding senior bits of the binary adder, the sum and transfer outputs of which are connected to the information inputs of the corresponding bits of the register. bShGPG ‘’ Tfs