SU1124317A1 - Logical processing device - Google Patents

Abstract

A LOGICAL PROCESSING DEVICE containing an address register,: an address decoder, an address transceiver unit, and a data transceiver unit, the first information input of which is connected to the device's information input, and the information inputs of the address register and address transponder unit are connected to the address input CTBi device, characterized in that, in order to improve performance, it contains a term storage unit, a function storage unit, a result storage unit, a reversible term counter, a reversible counter. IR functions, switch, result register, two one-shot, differentiating element, key, block of elements OR, five elements OR and three elements AND, with this first and second input of the first element AND are connected respectively to the first output of the address register and input controlling the device mode, the first and second inputs and the output of the second element I are connected respectively to the second output of the address register, the device mode control input and the counting input of the reversible term counter, the increment input, the input parallel behind- . The information input and information output of which are connected respectively to the information input of the device, the output of the first one-shot, the information output and the information input of the memory storage unit, the first and second inputs and the output of the first OR element are connected respectively to the output of the first -1 one-shot, mode control input device memory and the read input of the block (L memory of the result, write entry, address input, information input and information output of which are connected respectively to the output of the second the one-shot, the output of the OR block, the output of the result register and the first information input of the switch, the second information input, the control input and the output of the switch are connected respectively to the low-voltage output of the reversible function counter, the information input of the device and; the information input of the result register, whose synchronous input connected to the output of the first one-shot, the output, the first and second inputs of the third element And connected respectively to the input of the first one-shot, the second output address register and the output of the second element OR, whose inputs are connected to the information input of the device, the output, the first and second inputs of the third element OR

Description

connected, respectively, to the input of the access permission of the memory unit; the result; the second output is addressable; the first register and the output of the decoder, the first and second inputs of the OR block are connected respectively to the information input of the device and the first input of the address transmitters block, the second output and control input of which are connected respectively to the input of the address decoder and the second output of the address register, the first and the second inputs and the output of the fourth element OR are connected respectively to the first and second outputs of the address register and the input of the access permission of the thermal storage unit, the address input, the read input and the write input which are connected respectively to the address input of the device, the output of the first one-shot and the output of the fifth element OR, the first and second inputs of which are connected to the outputs of the first element AND the second one-vibration, respectively, whose input is connected to the output of the second element AND, the control input, the second information Hfctfi the input and output of the data transceiver unit are connected respectively to the second output of the address register, the code of the result storage unit and the information input of the memory storage unit, output, information An input input, a parallel recording input, an increment input and a counting input of a reversible function counter are connected respectively to the information input and output of the function memory, the output of the first single-oscillator, the information input of the device and the key output, the control input and information input of which are connected to the outputs respectively the second element AND of the differentiating element, the input of which is connected to the output of the higher bit of the reversible term counter, and the reading input, the write input, the address input and the resolution input rotating the unit memory functions are respectively connected to the output of the first monostable multivibrator, the output of the second monostable multivibrator, an address input unit and the second output of the address register.

The invention relates to digital computers and can be used in control microprocessor systems.

A logical processing device is known which comprises a one-bit processor, a memory device, a data port and a lj input device.

It is also known a logical processing device comprising a general-purpose microprocessor, a storage device, input / output devices and a logical decoder 2J,

These devices are designed to automatically control machines and production processes.

The disadvantage of these devices is the low speed in solving Boolean equations.

The closest to the present invention is a logic processing device comprising a processor, input devices, a memory, a switch, serial-to-parallel converters, and a fault detector. In a known device, cyclic polling of input channels is performed. The switch, upon command from the processor, selectively connects a group of inputs to parallel-serial converters, which perform data ordering to check the logical conditions. The logical conditions include variables corresponding to the polled channels h.

The disadvantages of the known device are low computation speed due to the fact that every time a full check of fulfillment of the conditions of Boolean equations and program formation of the result words is performed, and a large amount of memory for writing equations, as the memory is permanently stored of equations.  The purpose of the invention is to improve the performance of the device and reduce the amount of used memory.  This goal is achieved by the fact that a logical processing device containing a 1-address register, an address decoder, an address transceiver unit, and a data transceiver unit, the first information input of which is connected to the information input of the device, and the address transceiver unit is connected to the address input of the device, a term storage unit, a function storage unit, a result storage unit, a reversible term counter, a reversive function counter, a switch, a register are entered. result; two one-shot; differentiating element key, block of elements OR, five elements OR and three elements AND, with this the first and second inputs of the first element AND are connected respectively to the first output of the address register and the device control mode, the first and second inputs and output of the second element AND connected, respectively, to the second output of the address register, the device mode control input and the count input of the reversible term counter, the increment input, the parallel recording input, the information input and the information output of which are connected respectively, with the information input of the device, the output of the first one-vibrator, the information output and the information storage 4 input of the memory unit, the first and second inputs and the output of the first OR element are connected respectively to the output of the first one-vibrator, the mode control input input and the result memory unit input, Record input, address input, information input and information output of which are connected respectively with the output of the second one-shot, the output of the OR block, the output of the result register and n rvym data input switch, the second information. the input, the control input and the output of the switch are connected respectively to the low-order output of the reversible function counter, the information input of the device and the information input of the result register, the synchronous input of which is connected to the output of the first one-oscillator, the output, the first and second inputs of the third And element are connected respectively to the input of the first one-shot, the second output of the address register and the output of the second element OR, the inputs of which are connected to the information input of the device, code, the first and second inputs of the third The OR element is connected respectively to the output of the address access block of the result memory, the second output of the address register and the output of the address decoder, the first and second inputs of the OR block are connected respectively to the information input of the device and the first output of the address transceivers block, the second output and the control the input of which is connected respectively to the input of the address decoder and the second output of the address register, the first and second inputs and the output of the fourth OR element are connected respectively to the first and the output address register's mountain outputs and the address of the memory access of the memory unit of the terms, the input address, the read input and the write input of which are connected respectively to the address input of the device, the output of the first single-oscillator and the output of the fifth OR element, the first and second inputs of which are connected to the outputs of the first element respectively And the second one-shot, the input of which is connected to the output of the second element And, the control input, the second information input and the output of the data transceiver unit are connected respectively to the second the address register, the output of the result memory and the information input of the memory, the output, the information input, the parallel stroke, the increment input and the counting function of the reversible function counter are connected respectively to the info. The memory input and output of the function memory, the output of the first one-shot, the information input of the device and the output of the key, the control input and information input of which are connected to the outputs of the second element, respectively, and the differential of the lean element, the input of which is reversible the term counter, and the read input, the write input, the address input and the permission input of the function memory block are connected respectively to the output of the first single selector, the output of the second single selector, address input home device and the second output of the address register.  FIG.  1 shows a block diagram of the proposed logical processing device; in fig.  2 - switch circuit is functional; in fig.  3 - timing diagram of the device in the logical processing mode.  The device (FIG.  1 and 2) contains block 1 of memory of terms, block 2 of function memory, block 3 of result memory, reversible counter of 4 terms, reversible counter of 5 functions, result register 6, koshutator 7, system trunk 8, block 9 of data transceivers block 10 transceivers addresses, block 11 elements OR address register 12, the first and second elements OR 13 and 14, the first and second elements AND 15 and 16, the decoder 1 address, the third and fourth elements OR 18 and 19, the third element 20, . the first and second one-shot 21 and 22, the key 23, the fifth element OR 24, the differentiating element 25, the decoder 2 the first and second keys 27 and 28.  The term memory unit 1, the function memory unit 2, and the result memory unit 3 are memory devices whose cells, using a reversible counter of 4 terms, a reversible counter of 5 functions, and a result register 6, form virtual counters corresponding to conjunctive terms and a Boolean function m, and virtual result registers.  Term Memory Block 1 and Functional Memory Block 2 are connected to the account. A term and a counter of 5 functions are directly transferred, and the data from the result memory block 3 is transferred to the result register 6 via. switch 7.  The structure of the device is largely predetermined by the chosen method of solution. the Boolean equations, the main features of which are reduced to the following; the initial equations are presented in a disjunctive normal form; truth (equality of logical unit) separate conjunctive. the term in the equation is checked by counting the variables in it that currently have the value of a logical unit, and comparing the results of the count with the control constant; the truth of the boolean equation is verified by counting the conjunctive terms included in it, which currently have the value of a logical unit, and comparing the result of the count with the control constant.  Let us take as an example the equation Я / ЯгПe ГИЦЦЛЯ. P, 0) where f is a Boolean function; Ts boolean variables; q ,,, h, a pa conjunctive terms.  The control constant for the first and second conjunctive terms will be the number 3, and for the third - 2.  The control constant for checking the falsity of the function will be the number 6.  Each conjunctive term and each function corresponds to a virtual counter.  The control constant for all the counters corresponding to Boolean functions is O, Comparison of the values of the counters corresponding to conjunctive terms of the equations in this device is also performed with one constant common to all these counters.  As such a constant, we take the number corresponding to the highest bit of the counters used.  So for four-bit counters, such a constant would be the number 18.  This, in turn, means that for a given digit count, the maximum number of variables included in one conjunctive term should not exceed 8, and the number of conjunctive terms in one equation should be no more than 15.  In order to operate with a common control constant, the constants of initial values are preloaded into the counters of conjunctive terms, which are defined as the difference between the control constant and the number of variables included in this conjunctive 1st term.  So, with 71 received control constant 8, the initial value constants for the counters corresponding to the conjunctive terms of equation (1) are 5, 5, and 6.  The logic processing device is connected to the microprocessor system via system trunk 8, which, in particular, can have a three-bus organization (data width, address bus and mode control bus).  The first information input of block 9 is connected to the information input of the D device (bus data bus 8), and the information inputs of the address register 12 and block 10 are connected to the address input A of the device (bus address bus 8), the first and second inputs of the element 15 are connected respectively to the first You are running a register 12 and the device control mode control input Zp (bus mode control bus 8).  The first and second inputs and output of the element 16 are connected respectively to the second output of the register 12, the device mode control input and the counting input of the counter 4.  The increment input, the parallel recording input, the information input and the information output of the counter 4 are connected respectively to the information input of the DZ device, the one-shot 21, the information output and the information input of the block 1.  The first and second inputs and output of element 13 are connected respectively to the output of the one-shot 21, the control device control input H and the read input of block 3, the write input, the address input, the information input and the information output of block 3 are connected respectively to the output of the one-vibrator 22, output of the block 11, the output of the register 6 and the first information input of the switch 7, the Second information input, the control input and the output of the switch 7 are connected respectively to the low-order output of the counter 5 to the information input D2 of the device and information to the copy input of the register 6, the synchronous input of which is connected to the output of the one-shot 21.  Exit, first and second entrances. element 20 is connected respectively to the input of the one-shot 21, the second output of the register 12 and the output of the element 14, the inputs of which are connected to the information 78 input D of the device.  The output, the first and second inputs of the element 18 are connected to the access enable input of block 3, the second output of the register 12 and the output of the decoder 17, respectively.  The first and second inputs of block 11 are connected respectively to the information input D1 of the device and the first output of block 10, the second output and control input of which are connected respectively to the input of the decoder 17 and the second output of register 12.  The first and second inputs and output of the element 19 are connected respectively to the first and second outputs of the register 12 and the access enable input of block 1, the address input, the read input and the write input of which are connected respectively to the address input A1 of the device, the outputs of the one-shot 21 and the element 24.  The first and second inputs of the element 24 are connected to the outputs of the element 15 and the one-shot 22, respectively, the input of which is connected to the output of the element 16.  The control input, the second information input and the output of block 9 are connected respectively to the second output of the register 12, the output of block 3 and the information input of block 1.  An output, an information input, a parallel recording input, an increment input and a counting input of counter 5 are connected respectively to the information input and output of block 2, the output of the one-shot 21, the information input of the DZ device and the output of the key 23.  The control input and the information input of the key 23 are connected to the outputs of elements 16 and 25, respectively, while the input of the latter is connected to the output of the higher bit of the counter 4.  In this case, the read input, the write input, the address input and the access enable input of block 2 are connected respectively to the outputs of the one-shot 21 and 22, the address input A2 of the device and the second output of the register 12.  In switch 7 (FIG.  2) each of the outputs of the decoder 26 is connected to a control opening input of the first key 27 and a control closing input of the second key 28.  The flow of the decoder 26 is the control input of the switch 7.  The information inputs of the keys 27 are interconnected and with the second information input of the switch 7.  The information inputs of the keys 28 are the first information input of the switch 7.  The outputs of the keys 27 and 28, belonging to one bit, are connected to each other by themselves and. are the information output of the commutator 7.  To control the logic processing device from the side of the central processor of the microprocessor system, three commands are used: Output, Write to memory, Read memory (these commands are typical for microprocessors).  At the command Output, the processor writes into the register 12 a sign of the operation mode.  The device has three modes of operation: logical processing (the first output of register 12 is 1, the second is O); reading the words of the result (the first and second outputs of register 12 are O); write constants to the term meters (the first output of register 12 is O, the second is 1).  I On the Write to memory command, the processor writes the initial value constants to the conjunctive terms counters (in the Constant constants mode, writes the term counters) or sets the connected chain the term counter counter of the discharge function in the result word and determines in the device the operation is addition or subtraction 1 (in the Logic processing mode).  The command Read memory is used to output the values of the Boolean functions from block 3.  The device works as follows. at once, in. the beginning of the operation of the cell of block 2: and the register 12 of the processor of the system is zeroed at the command Vyshod for; the value of the sign of the mode of the working mode is written;  The signal from the second about the output of register 12 enters through element 19 and & block enable input t ,.  preparing it for work, and at the input element 15.  Then, the processor in the standard way, using the Write to memory command, sequentially loads into the cells of block 1, corresponding to the counters of conjunctive terms, the constants of the initial values.  In this case, the address input of block 1 receives the code of the address A1 of the corresponding cell, and according to the data through block 9, the value of the initial loading constant.  After loading the initial value constants with the next command Output, the operation mode is set to Logical processing.  This device is intended to work as part of a computer system in which, independently of the logical processing device, the change in the values of the variables included in the boolean equations is controlled. In the system (its control program) for each variable there is a list of conjunctive terms in which enters, and for each conjunctive term a list of functions. In addition, in the equations of which it enters, and also the addresses of the functions in block 3, the device receives information related only to variables that have changed their value.  When executing the Write to memory command on lines A1, A2 and D1 of trunk 8, address codes are set, respectively, of a term counter, which includes the current variable, a function counter, into the equation of which the term is included, and a result word, into which the calculated value is placed functions.  On lines D2, a code is set that defines the bit in the addressable result word for the variable value.  The value of the Addition – Subtraction signal supplied to counters 4 and 5 is specified via the DZ data line, to which the value of the logical unit is applied if the value of the current variable is 1 and the variable enters this conjunctive term without inversion or if the value of the current variable is Oh, and she enters this conjunctive term with inversion.  The value of a logical zero on the DZ line is supplied if the value of the current variable is O and it enters this conjunctive term without inversion, if the value of the current variable is 1 and it enters this conjunctive term with invarsi-, it.  The operation of the device in the Logic mode is explained in a time diagram (FIG.  3).  Execution of the Write to memory command from the excitation of address lines A1 and A2. In this case, in block 1 and block 2, access to the address cells is prepared.  Then excite data lines D1, D2 and DZ.  The code on the lines D1 selects the cell in block 3.  The signal on the DZ line sets the counting direction (1) of counters 4 and 5.  According to the code on lines D2, the number of the bit in which the value of the Boolean function is written is specified.  The total zero value of the signals on lines D1 and D2 is programmatically prohibited, so the signal 1 appears at the output of element 14 and the element 20 is energized. its output level changes from zero to one.  A positive front starts the one-shot 21, the signal from which is fed to the read inputs of blocks 1, 2 and 3, as well as to the write inputs of counters 4 and 5 and the synchronous input of register 6.  The data from the memory cells is rewritten to the indicated counters and register.  When the control line is excited Writing into the memory at the counting input of the counter 4 receives a signal and the counter performs the operation +1 or -1 depending on the value of the signal on the DZ line.  If a change occurs in the value of the most significant bit of counter 4, element 25 generates a signal which, via key 23, goes to the counting input of counter 5, which in this case also performs the +1 or -1 operation, the low-order value of counter 5, which is the value of the function of the solved equation is fed to the second information (corrective) input of the switch 7.  In switch 7 (FIG. 1, the signal from counter 5 is transmitted to the output on the bit in which at the control input of the switch 27 there is an enabling signal from the output of the descrambler. Torah 26.  The values of the remaining bits of the 1712 switch subdivisions correspond to the content of the 3 cells addressed in the block. From the output of the switch 7, the corrected result word is written to register 6.  The falling edge of the main signal is written to the memory. The one-shot 22 starts up, the signal from which is fed through the element 24 to the recording input of block 1 and to the similar inputs of blocks 2- and 3.  The corrected values of the term counter, function counter and result register are overwritten into the Psm cells, from which they are read.  The calculation of the functions of changing one variable in the composition of one term ends there.  The Write to Memory command is repeated for all terms that includes a variable, for all variables that have changed their meaning.  In control computing systems, control discrete signals are output, usually grouped by word or byte.  Therefore, in this device, the computation of Boolean functions is accompanied by the packing of the values of the functions into result words.  To read the result words, the CPU puts the device into the operation mode Reading the result words and using the Memory read command, in a standard way find the necessary data from block 3.  The technical advantage of this device in comparison with the known ones is an increase in processing speed (productivity) by 2-3 orders of magnitude and a decrease in the amount of used memory by 2-3 times.

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Claims (1)

A LOGO PROCESSING DEVICE containing an address register, an address decoder, an address transceiver block and a data transceiver block, the first information input of which is connected to an information input of the device, and the information inputs of the address register and address transceiver block are connected to the address input devices: characterized in that, in order to improve performance, it contains a term memory block, a function memory block, a result memory block, a reversible term counter, a reversible fun counter , switch, result register, two one-shots, differentiating element, key, block of OR elements, five OR elements and three AND elements, while the first and second inputs of the first AND element are connected respectively to the first output of the address register and the device mode control input, the first and second inputs and the output of the second element And are connected respectively to the second output of the address register, the input of the device mode control and the counting input of the reverse term counter, increment input, parallel recording input, inform Scintillation input and information output of which are respectively connected to the information WMOs> the device’s house, the output of the first one-shot, the information output and the information input of the term memory block, the first and second inputs and the output of the first OR element are connected respectively to the output of the first one-shot, the control mode of the device and the read input of the result memory block, write input, address input, information the input and information output of which are connected respectively to the output of the second one-shot, the output of the block of OR elements, the output of the result register and the first information input of the switch , the second information input, the control input and the output of the switch are connected respectively to the low-order output of the reversible function counter, the information input of the device and the information input of the result register, the sync input of which is connected to the output of the first one-shot, the output, the first and second inputs of the third element And are connected respectively to the input the first one-shot, the second output of the address register and the output of the second OR element, the inputs of which are connected to the information input of the device, the output, the first and the second inputs of the third OR element and _n „1124317 are connected respectively to the access enable address of the result memory block, the second output of the address register and the output of the address decoder, the first and second inputs of the block of OR elements ^ are connected respectively to the information input of the device and the first input of the receiver unit of the address transmitters, the second output and control input of which are connected respectively to the input of the address decoder and the second output of the address register, the first and second inputs and the output of the fourth OR element are connected to responsibly, with the first and second outputs of the address register and the input of the permission block of the term memory block, the address input, read input and write input of which are connected respectively to the device address address, the output of the first one-shot and the output of the fifth OR element, the first and second inputs of which are connected to the outputs, respectively the first element And and the second one-shot, the input of which is connected to the output of the second element And, the control input, the second information input and the output of the block of data transceivers are connected respectively Accordingly, with the second output of the address register, the output of the result memory block and the information input of the term memory block, the output, the information input, the parallel recording input, the increment input and the counting input of the reverse function counter are connected respectively to the information input and output of the function memory block, the output of the first one-shot, the information input of the device and the output of the key, the control input and information input of which is connected to the outputs of the second AND element and the differentiating element, respectively, the input which is connected to the high-order output of the reversible term counter, and the read input, write input, address input, and access enable address of the function memory block are connected respectively to the output of the first one-shot, the output of the second one-shot, the device’s address input, and the second address register output.