SU1112406A2 - Multichannel primary storage - Google Patents

Abstract

I. / PNOGOCHANNOE OPERATIVE ZAPO / CALCULATING DEVICE according to author. St. No. 1088067, characterized in that, in order to improve the reliability of the device, the first OR element and an additional logic block, whose inputs are connected to the same outputs of information input blocks, are entered into it, and the output is connected to one of the inputs of the first OR element, the other input of which is connected to the second output of the logic block, with the outputs of the additional logic block and the first element OR being one of the outputs of the device. 2. A device according to claim 1, characterized in that the additional logic block contains AND-OR elements and the second OR element, the output of which is the output of the block, and the inputs are connected to the outputs of the AND-OR elements, whose inputs are pairwise interconnected according to the principle There are two combinations of K (where K is the number of channels of the device) and are block inputs. to. o o)

Description

The invention relates to computing and is intended for use in multiprocessor-to-machine computing systems as a common RAM.

According to the main author. St. No. 1088067 known multi-channel random-access memory containing a drive, address current drivers, read amplifiers, information signal drivers, groups of OR elements, input and output channels, output channel signal distributor, input block selectors and logic unit, one of whose outputs is output devices, the outputs of the elements of OR groups are connected to the inputs of the corresponding address current drivers, the outputs of which are connected to the drive input addresses, the outputs p the signal distributor of output channels is connected to the inputs of information signal shapers, the outputs of which are connected to the information inputs of the accumulator, the outputs of which are connected to the inputs of the read amplifiers, the first input channel contains the first and second address registers, the first and second address decoders, the outputs of which are the first and second outputs input channel, and the distributor of signals, the outputs of the first and second address registers are connected to the inputs of the signal distributor, the first and second outputs of the input the first channels of the output channels to the outputs of the read amplifiers, the second inputs of the second and subsequent output channels to the third outputs of the corresponding input channels, the first outputs of the output channels to the inputs of the signal distributor of the output channels, the first input the channel contains three groups of And elements, and the outputs of the first and second address registers are connected to the first inputs of the And elements of the first and second groups, the outputs of which are connected to the inputs of the first and second decoders a The outputs of the signal distributor are the fourth output of this channel and connected to the first inputs of the elements of the third group, whose outputs are the third output of the first input channel and connected to the second input of the first output channel, the second inputs of the AND elements are connected to the third input of the first input channel , the third inputs and the fourth outputs of the input channels to the first outputs and the first inputs of the selectors, the second outputs of the selectors to the inputs of the logic unit, the other outputs of which are connected to the second inputs of the village tori selectors third inputs - outputs to the respective data input blocks. A disadvantage of the known device is the low accuracy of control of its channel priorities, which reduces the reliability of the device. This is due to the fact that conflicting calls, consumer devices (processors) are monitored and the correctness of the priority setting of its channels is not monitored, as a result of which uncertain situations and failures can occur. So with the discrepancy of the address codes at the device inputs and / or with the discrepancy between the codes and the outputs of the signal distributors

The device does not detect incorrect channel priority setting. It should be noted that in this case it does not affect the operation of the device. However, when a logical unit level appears at the output of a logic unit, it is not clear whether this level arose only due to conflicting processors, which does not affect the continued operation of the device, or due to conflicting processors and incorrect priority setting, which causes to failure and requires operator intervention in the operation of the device. The aim of the invention is to increase the reliability of the device.

The goal is achieved by the fact that

the first OR element and an additional logic block, whose inputs are connected to the same outputs of information input blocks, are entered into the multichannel random access memory, and the output is connected to one of the inputs of the first OR element, whose other input is connected to the second output of the logic block, and the outputs of the additional logic block and the first OR element is one of the device outputs.

In this additional logical

The block contains elements AND-OR and BTO. the OR element, whose output is the output of the block, and the inputs are connected to the outputs of the AND-OR elements, whose inputs are pairwise interconnected according to the principle

There are two combinations of K (where K is the number of channels of the device) and are block inputs.

FIG. 1 and 2 shows a block diagram of the device; in fig. 3 is an electrical circuit of an additional logic unit; in fig. 4 is a block diagram of the input channel; in fig. 5 is a block diagram of the output channel; in fig. 6 - functional logic block; in fig. 7 -

electrical selector circuit; in fig. 8 is an electrical circuit of an information input unit.

Multichannel random access memory (Fig. 1 and 2) contains a drive 1, shapers 2i and 2j address

currents, amplifiers 3 readings, shapers 4 information signals of group 5, to 5g elements OR, input channels 6i-6k output channels 7, -7k, distributor 8

output channel signals, logic block 9, selectors lOi - 10k, lit blocks - UK information input, resistor 12, additional logic block 13 and first element OR I. Input channels 6i-6k have first 15 | -15k, second I6 | - 16g and the third I7t - 17k inputs, the first I8i-18k, the second 191-19k, the third 20i-20 k and the fourth 211 - 21k outputs. The output channels have the first 22i-22k, the second 23 -23k third 24t-24k inputs and the first 25i-25k and the second 261-26k outputs. Logic block 9 has inputs and the first 28t-28it-i and the second 29 outputs. Selectors 10% -Yukimeyut first 30i-ZOK and the second and first 32, second and third 341 - 34l inputs. Blocks Ih - 11k input information have outputs 35i-35x. Unit 13 has inputs 36i-Zbk outputs and output 37. Output 38 of the element OR 14 is one of the outputs of the device. The other output of the device is the output 37 of the additional logic block 13. The additional logic block 13 (FIG. 3) contains the elements AND-OR 39v-39k and the second element OR 40. The outputs 411-41x of the AND-OR elements are connected to the inputs of the second element OR 40 .

Input channel 6 (Fig. 4) contains the first 42 and second 42g address registers, the first 43j and the second 43g address decoders, the signal distributor 44 and the three groups of I elements. The output channel 7 (FIG. 5) contains a switch 46, a word register 47 and a channel signal distributor 48. Logic block 9 (Fig. 6) contains AND 49 elements, blocks 50 "-50m, 50a, 50g4 and 50m comparisons and the element OR 51. Indices in the designation of comparison blocks indicate combinations of their input numbers. For example, Comparison Unit 50 has a combination at the input of inputs 27 and 27z. The selector 10 (FIG. 7) contains an Element 1 and 52 and an AND-OR element 53. The information input unit II (FIG. 8) contains a K-module switch 54 with dependent latching and a common reset button and resistors 55i-55i and 56.

The proposed device works in much the same way as the known device. It is similar to setting channel priorities, and also the properties of valves 44 completely coincide. Therefore, the device operation is described in two cases covering all events of interest to us: first, the mismatch of the codes at the outputs of valves 44 | -44 of input channels 6t-6k as a result, if the address codes received at the entrances do not coincide, 15i -15k and 16 | -16k devices; secondly, the coincidence of the channel address codes or the coincidence of the codes at the outputs of the 44i-44k distributors with the mismatch of the channel address codes at the inputs I5i -15k and 16., - 16i devices.

At the inputs I5i -15k and I6i -16k channels, addresses of words to be randomly or simultaneously processed (read and / or written) and the maximum number of which, when processed simultaneously, are equal to the number of device input or output channels, are given.

If the codes at the outputs of the distributors 44t-44k do not coincide and, as a result, if the address codes received on the input channels 6i-6k of the device (first case) do not match, the input 6t-6k and output channels of the device are completely independent and allow simultaneous reading and / or writing words. Since the indicated codes do not coincide, the inverse outputs of all comparison units 50 (Fig. 6) will have levels of a logical unit that, passed through the elements of And 49 and the selectors (Fig. 7), are fed to the inputs of the elements And 45i-45k of the input, channels 6) -6 k as permitting levels. Let us consider in detail the passage of signals through the first input 6i and output 7i channels of the device, since the passage of signals through all other input and output channels is similar to passing through the first.

Upon receipt of the address code to the inputs

0 15 | and 16i of the first input channel 6 "from the output of the registers 42 and 42 (Fig. 4), the address codes go directly to the inputs of the distributor 44 and the decoders 43 and 43 of the address through the previously opened elements And 45i and 45g. From the outputs of the address switches 43i and 43g of the address through the elements OR 5i and 5g (Fig. I), the signals arrive at the inputs of the formers 2 and 2j. As a result, storage elements will be selected at the corresponding inputs of accumulator 1, and .. the first word read will arrive at the inputs of amplifiers 3. The distributor 44i in accordance with the contents of the registers 42 to 42 connects the amplifiers 3 through the switch 46i to the register 47 of the first output channel 7i (Fig. 5). Thus read

5, the first word from accumulator 1 arrives at information output 26j of the device. All other channels work in the same way. In this case, at output 29 of block 9 and at outputs 37 and 38 of the device there are no levels of logical zero, indicating that there are no failures in the device. The output 29 of block 9 and the output 37 of block 13 will be the levels of logical zero due to the fact that all the inputs 27t-27, block 9 and block 13 will be given mismatched codes. 5 Since the outputs 29 and 37 of blocks 9 and 13 are current / on the inputs of the element OR 14, then at the output 38 of this element there will be a logical level, witnessed

There are no failures in the device.

GTrede than to describe the further operation of the device, by setting the priorities of the channels.

The prioritization of the channels is accomplished, the outcome of the following considerations:

1. The lower number of the mod. - switch 54 of block 11 (in Fig. 8 is the leftmost one) corresponds to the highest priority and narobot.

2. Turning on the required switch module 54, the priority is set to the appropriate channel.

3. In all channels of the device, different (non-coincident) priorities should be established. Setting the same priority in at least two channels is unacceptable, since in case of coincidence of codes at the outputs of the data channel allocators 44 of the input channels, a failure occurs in the device.

4. iOt - Yuk selectors under the control of Hf - And k blocks provide the required switching of the outputs 44i – 44k of input channels 6 "-6 and to the inputs 27t-27k of block 9 and, consequently, to the inputs of the blocks, 50tv-50 ((. F , K comparison (for a four-channel device - 50 (4, 50 C 50 j).

5. When arriving at inputs 27 / .- 27 "t, block 9 of coincident codes due to coincidence of address codes at inputs iSj - 15k 41 16} -16k and / or at the outputs of distributors 44) -44k of input channels 6t-6k at outputs 28, -28k-1 block 9 appears k-1 prohibiting levels of logical zero.

6. In accordance with the installed switching of inputs 27i-27k k-1 of prohibiting levels of logic zero from outputs 28) -28k- | unit 9, through selectors lOi-10k, to the corresponding input channels GI-bk. to the channels of the device. In this case, the only unblocked channel will be the channel with the highest priority. The resolution level of the logical unit for it is transmitted from the power source Enin-through resistor 12 (Fig. 2) and the AND-OR 53 element (Fig. 7) of the corresponding selector 10.

If the address codes received at the inputs 15–15k and 16–16k and / or the codes at the outputs of the 44i-44k distributors of all input channels 6 | -6k are completely identical, only one well-defined input channel and its corresponding output channel will be opened. All other channels will be blocked. In this case, as has been shown, the open channel will be the one that is connected to the Epig power source. through a resistor 12.

In case of partial coincidence of the address codes and / or codes at the outputs of the distributors 44

Some input channels all other channels are open and operate independently of each other. Those channels in which the indicated codes have coincided are blocked.

 with the exception of one - the channel with the highest priority. In this case, at the output 29 of block 9, the level of a logical unit appears, indicating that the codes in the device have coincided.

As it was mentioned, if there is a mismatch between ko0dov on the outputs of the 44i-44kN distributors, as a result, if the address codes received on input channels 6 (–6 to (first case) input 6, –6k and output 7t-7k channels of the device completely mismatch

j are independent, and block 13 and the element OR 14 have no effect on the operation of the device.

The block 13 and the OR 14 element with the appropriate connections affect the operation of the device only when the codes coincide (full or partial), and ensure the detection and localization of incorrectly set priorities of the device channels.

c. So, if priorities are set incorrectly in two or several channels, for example, switch modules of the same name 54 in the corresponding blocks 11 (for example, modules 35i in the first P and second llj blocks), then the same priority belongs simultaneously to two or several channels (in the example above, the same priority belongs to the first 6.1 and second 6g channels). Therefore, if there are conflicting (simultaneous) handling of processors to these channels, i.e. by address, whose codes match at the outputs of the channel allocators 44, the required channel blocking does not occur, although at the output 29 of block 9 a logical unit appears, testifying to

what happened in the device matching the codes. The absence of the required channel lock leads to failure, since all channels with the same priority remain unlocked (in this example, channels 6 | and 6 are unblocked),

5, and therefore two or more processors are addressed to the same addresses or to addresses whose codes differ in the rearrangement of their halves (for example, OPOI codes 10 and 11100110). This is not allowed and is detected by block 13. Equal priority levels from the outputs of blocks II (in our example, the levels of the logical unit from outputs 351. blocks 111 and I 1g) are fed to the inputs of block 13 (to inputs 36i, respectively). As a result, at one of the exits

J 41 (-41 cells AND-OR 39i-39kpo is the level of the logical unit (in this case, the output of the 411 element AND is OR 39i). Passing the element OR 40, the level of the logical unit appears at the output 37 of block 13 and signals about a device failure. If other similar-source moauli switches of 54 different blocks II are turned on, then the output of another, well-defined AND-OR element of block 13 is the level of a logical unit, indicating a failure in the device. Thus, the lack of levels of a logical unit at output 29 of block 9, at output 37 of block 13 and the output 38 of the element OR 14 indicates the absence of failures and coincidence of address codes when accessing the device.In this case, all the channels of the device operate independently, providing arbitrary or simultaneous processing of information on the channels.When there is a logical unit level at output 29 of the block 9 and, consequently, at the output 38 of the element OR 14 and in the absence of a level of logical units at the output 37 of the block 13 in the device there is a conflicting reversal of the processors. Priority is given to the processor connected to the channel with the highest priority. The remaining processors are temporarily locked, the device continues operation. If there is a level of logical units at output 37 of block 13 and. therefore, at the output 38 of the element OR 14 in the device, the prioritization of the channels takes place incorrectly, which can lead to a malfunction if the processors conflict. In this case, the operator’s inclusiveness is required. The technical advantage of the proposed device compared to the known one is the ability to localize improperly set priorities and report it to the system and / or operator using levels of a logical unit. Ultimately, this increases the degree of autonomous and system control and simplifies troubleshooting.

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Claims (2)

I. MULTI-CHANNEL OPERATIONAL MEMORY DEVICE by ed. St. No. 1088067, characterized in that, in order to increase the reliability of the device, the first OR element and an additional logic block are inserted into it, the inputs of which are connected to the outputs of the same input information blocks, and the output is connected to one of the inputs of the first OR element, the other input of which is connected to the second output of the logical block, and the outputs of the additional logical block and the first OR element are among the outputs of the device. 2. The device according to π. 1, characterized in that the additional logical block contains AND - OR elements and a second OR element, the output of which is the output of the block, and the inputs are connected to the outputs of the AND - OR elements. the inputs of which are pairwise interconnected according to the principle of combinations "from K in two" (where K is the number of channels of the device) and are the inputs of the block. Fig t