SU1108528A2 - Frequency relay - Google Patents

Abstract

FREQUENCY RELAY on auth. St. No. 982114, in order to eliminate vibration at input frequencies close to the setpoint, a comparator and a voltage divider connected to the output of the pulse expander are additionally introduced, and the inverting input of the comparator is connected to the output of the second pulse shaper, non-inverted - to the midpoint of the voltage divider, the output of the comparator is connected to the reset input of the D-flip-flop, and in addition the pulse shaper is designed as a limiter amplifier.

Description

The invention relates to devices for relaying and automatics of power systems. According to the main author. St. 982114 known frequency relay containing split three} format, a low-pass filter, a resonant filter, two square drivers, a logic block, a logic element, a pulse spreader inhibition, and an actuator, in which the logic element is executed as a D-trigger, whose synchronization input is connected to the direct output of one driver, and the reset input is connected to the inverse output of another square pulse generator, and the information input of the D-flip-flop is connected to the newly entered voltage source 17 The return rate of such a relay is equal to unity, therefore, at frequencies of the input signal close to the frequency of the setpoint, the relay may vibrate. The purpose of the invention is to eliminate the vibration of the relay at frequencies close to the setpoint. The goal is achieved by the fact that in a frequency relay containing an isolation transformer, a low-pass filter, a resonant filter, the first and second drivers of regular impulses, the Inhibit logic element, the expander impulses and the actuator, the Prohibition element is in the form of a p-flip-flop, the synchronization input of which is connected to the direct output of the first former, and the reset input to the inverse output of another rectangular pulse former, and the information input of the D-flip-flop is connected to the source In addition, a comparator and a voltage divider connected to the output of the pulse expander are added, the inverting input of the comparator is connected to the output of the second pulseformer and non-inverting to the midpoint of the voltage divider, the output of the comparator is connected to the D-trigger reset input, and the second the pulse former is made in the form of a limiter amplifier. FIG. 1 shows a diagram of the proposed frequency relay; in fig. 2 timing diagrams explaining the operation of the down-frequency relay. The frequency relay contains a separating transformer 1, an input filter, a resonant filter 3, a first shaper 4 rectangular pulses, a second shaper 5 rectangular pulses, designed as an amplifier, a limiter, a D-flip-flop b, a voltage source, an expander 8 pulses an output element 9, comparator 10, divider 11 voltage. A controlled AC voltage U is applied to the relay input, which, through the input filter 2, eliminating the influence of the harmonic components of the input voltage on the relay operation, goes to the resonant filter 3. Sine-wave signals at the input and output of the filter 3 Uj and and, shifted in phase relative to each other by an angle depending on the frequency of the input signal U. transformed by shaper 4 and 5 pulses into common-mode square signals Ts and Uj, In the absence of an input voltage, the output signal (L of the first shaper impulses have a constant level, therefore, the output signal and, D-flip-flop b also has a constant level, respectively, the output signal of the expander 8 pulses is zero. The output organ is in an unworked state. In the case of a controlled voltage frequency f more than the setpoint frequency of the relay t, the voltage Uj lags in phase from the voltage Uj (Fig. 2a). In this case, during the pulse edge and at the synchronization input of the D-flip-flop at its reset input, the voltage U is high. Therefore, the voltage level at the output of the D-flip-flop 6 and, -a and the voltage level at the output of the expander 8 pulses Ug are kept low and the output organ 9 remains in an unheated state. By lowering the frequency of the monitored voltage f. below the setpoint frequency, t (Fig. 25) at the time of the pulse front at the synchronization input Dtrigger 6, the voltage at the D-flip-flop input is low, D-flip-flop 6 is set to one. After the voltage level is increased, the D-flip-flop will be reset to the zero state. Thus, when the monitored voltage decreases below the setpoint frequency, the output of the O-flip-flop will produce square impulses that will trigger the expander 8 of the pulses and the output element 9. To ensure reliable operation of the relay at frequencies of the controlled voltage close to the setpoint frequency , the comparator 10 and the second voltage divider 11 are additionally introduced. Each switch of the comparator 10 occurs when the voltage of the driver 5 reaches a threshold level determined by the voltage and at the non-inverting input. When a relay fails, the voltage is zero, and after the expander 8 is triggered it rises. Therefore, the switching of the comparator 10 will occur only when the voltage Uj reaches the voltage value and. Accordingly, the switching time of the comparator 10 will shift in time by an amount dt equal to the rise time Uj to and, the latter is equivalent to introducing an additional time shift between the signals U4 and and, to compensate for which (when the relay returns), it is necessary to increase the frequency

the input signal is up to some value f; j, exceeding f t- The value of af fi is the frequency hysteresis.

Thus, in comparison with the known, due to the introduction of hysteresis in frequency, the relay operates reliably at frequencies of the controlled network close to

to the setting value of the relay.

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Claims (1)

FREQUENCY RELAY St. No. 9882114, characterized in that, in order to eliminate vibration at input signal frequencies close to the setpoint, a comparator and a voltage divider connected to the output of the pulse expander are additionally introduced into it, and the inverting input of the comparator is connected to the output of the second pulse shaper, non-inverting - to the middle point of the voltage divider, the comparator output is connected to the reset input of the D-trigger, and the second pulse shaper is made in the form of a limiter amplifier. -J Fie1