SU1104512A1 - Random number generator - Google Patents

Abstract

A GENERATOR OF RANDOM NUMBERS containing a noise source, the output of which is connected to the information input of the first amplifier, the output of which is connected to the D input of a D-flip-flop, the output of which is connected to the input of the second amplifier, the output of which is the generator output, a clock generator, the output of which is connected with the C input of a D-flip-flop and with the first input of the PI element, a code register whose output is connected via a digital-to-analog converter to the control input of the first amplifier, characterized in that, in order to improve the accuracy, It contains a reversible counter, the information output of which is connected to the information input of the code register, the synchronization input of which is combined with the input. Installation of the reversible counter and connected to the output of the I element, the second input of which is connected to the overflow output of the reversible counter, the counting input of which is combined with the C input D a trigger, the output of which is connected to the control input of a reversible counter.

Description

four; The invention relates to specialized computing, in particular to computing systems with a probabilistic representation of information, and can be used as machine variables in devices for processing parameters of random processes. A known random pulse generator, comprising a pulse generator, a noise source connected to the counter input, the outputs of which are connected to the decoder, a switch, the control input of which is connected to the output of the decoder, and outputs to the counter installation inputs, and an adjustable counter, counting the input is connected to the output of the noise source, the control input is connected to the output of the pulse generator, and the outputs are connected to the inputs of the switch lj. The disadvantage of this generator is that the principle of stabilization of the intensity of the output pulses in it is based on an automatic reduction of the intensity to a certain minimum value, which inevitably leads to a decrease in speed. In addition, these devices do not provide equal footing of the distribution law and cannot be implemented using integral technology due to the presence of reactive elements. The known devices have a high level of power consumption and low operational reliability. A random number generator is also known that contains a sequentially connected noise source, a video amplifier and a memory device, serially connected driver and code generator of pulses, as well as a generator of gating pulses, voltage converter. frequency, number generator and power amplifier 2j,. The known device has a low operational reliability, low speed, does not provide an equipotent law of the distribution of numbers and cannot be implemented using an integrated technology due to the presence of reactive elements. The closest to the proposed technical essence and the achieved positive effect is a random number generator containing a serially connected noise source, a video amplifier and a memory device, serially connected shaper codes and shaper pulses, as well as a generator of gating pulses, power amplifier and serially connected element And, unit counter, correction register and digital-to-analog converter, while the information input of the AND element is connected to the output in the memory and the input of the power amplifier, the output pulse shaper connected to the inputs of the initial installation codes and shaper units counter and the correction to the data input of the register, and strobiruyush 1x pulse generator output coupled to an input of the counting codes and a clock input of the memory device. In the known device, the accuracy of the analysis of the uniformity of random numbers received by the output of the generator, and the accuracy of maintaining their uniformity are proportional to the size of the unit counter and the former. So, if a random sequence at the output of a random sequence generator (GSP) is characterized by some deviation from the uniformity e PI-PO, (1) where P and PO are the probability of occurrence of logic signals 1 and O at the output of GSP, then the mathematical expectation of the number of logical signals 1 after the occurrence of N bits of a random sequence should be M,., f (1 + f). The actual number of logical signals 1 contained in the N bits of a random sequence Q, is different from M, and the sign of the difference (Q (.f (-) only with some likely P corresponds to the sign of €. The probability that the value of Q. is in the range of (M. c - N) to (M, c + Ng), (i.e. the sign of the difference N (Qvv t) characterizes the sign) is determined by the Laplace theorem. Calculations show that to estimate a mark with a confidence of 0.95 for jEl 1СГ, it is necessary to recalculate the number of units in 6,710 bits of a random sequence, and for the case of IEI 1 (G in 6,740 bits.) counters with a capacity of 16 and 23 bits, respectively, which significantly complicates the RNG circuit. In the known RNG, the signal arriving at the correction register is periodically interleaved at intervals equal to the time taken to fill the counters. Thus, the more accurate the information about deviation from the uniformity is required, the greater must be the size of the counters, the more complicated their design and the longer the measurement process, i.e. the equilibrium value is less often corrected. If we take the value of the clock frequency ff 1 MHz, then the filling time of the counters of the known RNG when evaluating the sign (and | Е) -10 with a confidence of 0.95 for the described conditions will be 0.67 s and 67 s, respectively, and these time periods do not depend t from the real value of deviations -. With a significant deviation from the uniformity of a random sequence, the correction circuit of a known RNG can restore the uniformity in several correction cycles, which requires a considerable amount of time, since the correction circuit changes the correction signal in one cycle by a small value S. This limits the ability of the auto-tuning system to the uniformity of random numbers, since external factors affecting deviation from uniformity (ambient temperature, supply voltage, component aging processes, etc.) change at some finite rate, resulting in the formation rate The correction signal must be the rate of the indicated changes, as otherwise the deviation from the randomness uniformity will be from the maximum permissible value. Thus, the effect of external destabilized factors limits the size of the unit counter and the code generator, which inevitably degrades the accuracy of autotuning the randomness of random numbers. Increasing the accuracy of the auto-tuning within the limits of this limitation requires a significant increase in the capacity of the unit counter and the code generator, which complicates the design and reduces its reliability, and a further increase in the auto-tuning accuracy is possible only with decreasing speed. For example, the summation of two consecutive bits of modulo 2 results in a two-fold decrease in the speed of the RNG. Even with ideal equilibrium of random numbers, the correction signal in the RNG is produced and periodically changes the content of the correction register, which causes an increase in the autocorrelation coefficient of a sequence of random numbers. For constructing complex probabilistic automata, for example, stochastic supermixing devices, multichannel or multi-bit RNGs are used, and RNGs have the highest speed, which each bit of a random binary number is formed by a separate random binary sequence generator (GFR). , or several chips, which significantly reduces the cost and improves the operational characteristics of the RNG. At the same time, the most complex and occupying the largest part of the chip area of the chip is the auto-tuning block of equal numbers of random numbers. The most effective use of a single auto-tuning unit with several GPS in the RNG is such that the correction of the equilibrium of all the GPS is performed alternately with high speed, which is practically impossible in the well-known RNG. The purpose of the invention is to increase the speed and simplify the design of the RNG while improving the uniformity characteristic of a random sequence. The goal is achieved by the fact that a random number generator containing a noise source, the output of which is connected to the information input of the first amplifier, the output of which is connected to the D input of a D-flip-flop, the output of which is connected to the input of the second amplifier, whose output is

the generator output, the clock pulse generator, the output of which is connected to the C input of the D-flip-flop and the first input of the element I, the register of the code whose output through the digital-to-analog converter is connected to the control input of the first amplifier, is entered a reversible counter, the information output of which is connected to the information the input of the register of the code, the synchronization of whose input is combined with the input of the installation of the reversible counter and connected to the output of the element I, the second input of which is connected to the output of the overflow of the reversing center tchika, the counting input of which is combined with the C-input of D-flip-flop, whose output is connected to a control input reyersivnogo counter.

FIG. 1 shows a block diagram of a generator; Fig 2 - .time diagrams of the generator; Fig. 3 and A show the comparative characteristics of the parameters of the auto-tuning systems of the known and proposed generators.

The generator contains a source of 1 noise, an amplifier 2, a D-flip-flop 3, an amplifier 4, an element 5I, a register 6 of a code, a digital-to-analog converter 7, a generator of 8 clock pulses, a reversible counter 9.

The generator works as follows.

The noise voltage produced by noise source 1 is amplified by amplifier 2 (Fig. 2a) and is fed to the input of a D-flip-flop with a certain threshold. At the same time, pulses are received at the clock input of the O flip-flop 3 from the generator output of 8 clock pulses (Fig. 26). on the negative edge of which a logical signal 1 is recorded in the D-flip-flop 3, if the noise voltage at the moment has exceeded the threshold value or the logical signal O (Fig. 2c), if the noise voltage has not reached the threshold value. Binary information from the output of the D-flip-flop 3 through the amplifier 4 is output. At the same time, the binary information from the output of the D-flip-flop 3 is fed to the control input of the reversible counter 9. The clock input of the reversible counter 9 from the generator output 8 clock pulses are received by the action of which the content of the reversible counter 9 increases or decreases by one depending on the information supplied to the control input of the reversible counter 9 (Fig. 2d). At the initial moment in the reversible counter 9 is written N

N is the capacity of the counter.

the number is - where

During operation, the contents of the reversible counter 9 vary in some way and at the moment when the reverse counter contains O or N, the output of the overflow appears to be high (Fig. 2e, time t), and the information output shows high or low level depending on the presence of N or O in a reversible counter. Under the influence of a high level from the overflow output of the reversible counter 9 at the output of element 5, an impulse is produced (Fig. 2e), on the leading edge of which the contents of register 6 increase by one in the event that From the information output of the reversible counter 9 a logical signal is received at the register 6 or the contents of the register are reduced by one, if the information output of the reversible counter 9 to the register 6 receives a logical signal 1 (Fig. 2g, time). On the falling edge of the pulse coming from the output of element 5 AND, the reversible counter 9 is reset, after which a low level appears at its output and a new correction cycle begins (Fig. 2d, f, time to).

Let us consider in more detail the work of the correction system of the proposed RNG. Let the random sequence at the input of the reversible counter 9 be characterized by some deviation from the equality f P - PO OV In this case, the probability of filling the reversible counter 9 will exceed the probability of its zeroing, and the probability that the state of the reversible counter 9 at the end of the correction cycle corresponding to sign E, is the probability of a correct sign estimate and depends on the value of | t (and the capacity of the reversible counter.

The capacity of the reversible counter, necessary for evaluating the sign with a certain reliability, increases with decreasing magnitude and with increasing confidence of the estimate. The required value of the capacity of the reversible counter is calculated by the following method. In accordance with the Stirling formula, the probability of occurrence of m units at the output of the GPS after N. ticks is - (m-Npi1 2NPoP, l12mMr p) If in formula (3) to take the reversible counter capacity, the value will express the probability of filling the reversible counter on the N-OM cycle of a random sequence. The probability of filling the reversible counter after the N cycles of a random sequence will be equal to the sum of the probabilities of filling it in all the preceding ones. At the same time, it should be noted that the probability of filling the reverse counter on the Nj-th It is equal to the product of the probabilities of the actual filling of the counter multiplied by the probability that the counter will not be filled in all preceding 1 cycles. The principle of calculating the required value of the capacity of the reversing counter is the sequential summation of the probabilities of filling the reverse counter in general and its filling, where the contents correspond to the € sign. Calculate the dependence of the required capacity of the reversible counter and the analysis cycle time on the value 6 for the probability of a correct estimate of P 0.95 izvodits on a computer. FIG. 3 shows the dependences of the required number N of the binary bits of the counter in the correction unit on the deviation from the uniformity for the known RNG (curve A) and on the proposed RNG (curve B), and FIG. 4 dependence of the time required for one step of the correction cycle at a clock frequency f 1 mHz, on the deviation from the uniformity b1 for the known RNG (curve A,), and for the proposed RNG (curve B). Referred to FIG. 3 and A, the comparative characteristics of the parameters of the auto-tuning systems show that for 1 to 10 and the probability of a correct decision in the correction cycle P 0.95, the capacity of the Lvoic counter of the known RNG necessary for the binary bits must be 3.5 times greater than the capacity reversible counter of the proposed RNG, and the time spent on one step of the correction cycle in the known RNG is 4.5 times longer than the time required for the same Operation in the proposed RNG. The technical advantages of the RNG are that the 3.5-fold reduction in the capacity of the reversing counter allows the correction scheme to be simplified by the same factor, which is of great practical importance, since it is the correction scheme that determines the complexity of the RNG circuit, its reliability, speed and other tactical and technical indicators. A 4.5-fold reduction in the time spent on a single step of the analysis cycle allows for the operation of a discharge GSCH in such a way that one correction alternately serves several random sequence generators (GSP) of the random sequence parameters, and also significantly reduces the influence of external destabilizing factors. on the uniformity of a random sequence. The advantage of the proposed RNG is that, with a fixed capacity of the reversible counter, the analysis time decreases with increasing 6. This makes it possible to significantly reduce the time required to restore the required uniformity with a sharp deviation due to the influence of external destabilizing factors. So, in the well-known RNG, the time of one analysis cycle depends only on the capacity of the unit counter and the code generator. With a sharp discontinuous deviation from the equilibrium of the output random sequence required for, the recovery of the equilibrium time can reach a considerable value. For example, at f-r 1 MHz, the duration of the analysis cycle is necessary to maintain a value of € 1 10 for the known RMS 67 s, and for the RNG proposed 15 s. If for some reason the magnitude changes abruptly to y.

then the duration of the analysis cycle in the proposed RNG will decrease to 6.6 s, while in the known RNG it will remain unchanged.

Application of the proposed RNG in computing devices with probability

110451210

. presenting information will significantly improve their reliability, efficiency, increase speed, performance and accuracy, simplify the design and improve the equilibrium characteristic of a random sequence.

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Claims (1)

RANDOM NUMBER GENERATOR, containing a noise source whose output is connected to the information input of the first amplifier, the output of which is connected to the D-input of the D-trigger, the output of which is connected to the input of the second amplifier, the output of which is the output of the generator, the clock generator, the output of which is connected with the C-input of the D-flip-flop and with the first input of the And element, a code register whose output is connected via a digital-to-analog converter to the control input of the first amplifier, characterized in that, in order to increase accuracy, it contains there is a reversible counter, the information output of which is connected to the information input of the code register, the synchronizing input of which is combined with the “Setting” of the reversible counter and connected to the output of Element I, the second input of which is connected to the overflow output of the reversible counter, the counting input of which is combined with C -input of the D-flip-flop, the- Q output of which is connected to the control input of the reversible counter. 1 1104512