SU1100746A1 - Error detecting device - Google Patents

Abstract

A DEVICE FOR DETECTING ERRORS, containing in series, connected input block, block, faer, gating block, first mismatch counter and element joint. the fall, to the second input of which the output of the second mismatch counter, the input of which is connected to the output of the gating unit, is connected, the series-connected integrator, the assembly element and the memory register; as well as an error detection unit, as indicated. so that, in order to increase reliably., a serially connected key, a combination sensor, a first modulo two adder, an element I, a second modulo two adder and a first switch, and a serially connected second switch and an inhibition element, whose output connected to the second input of the assembly, to the third input of which the output of the error detection unit is connected, to the input of the KOTOpoiro the output of the first switch is connected, the second input of which is combined with the second input of the memory register, secondly the input The two modulo-two adders are connected to the second output of the first mismatch counter, the third input of the first switch is combined with the third input of register i memory, the first key input, the first input of the second switch and under (L is connected to the second output of the phasing unit, the first the output of the second switch is connected to the second input of the element I, the output of the memory register is connected to the second input of the key, and the second output of the second switch is connected to the input of the integrator, and the output of the first modulo two are connected to the direct input of the prohibition element. . ... ki 4 s

Description

The invention relates to a data transmission technique and can be used in information protection devices against errors of transmission systems with decision feedback (ROS).

A device for correcting errors in a code combination is known, which contains single-threshold and two-threshold blocks connected to the input of the device, a modulo-two adder, one input of which is connected to the output of the error polynomial formation unit and another input through successively connected buffer and main memory blocks to the output of the single-threshold block and the output of the modulo-two adder is connected to the first input of the element I, an error detection unit, the first output of which is connected to the output of the device. The second output is with the second input element And, the output of which is connected to the second output of the device, and the output of the two-threshold block is connected to the first input of the Error polynomial formation unit, the second input of which is connected to the second output of the error detection block, the output of the modulo-two is connected to the input error block through the OR element, the other input of which is connected to the output of the buffer memory block, the output of the modulo two adder is connected to the auxiliary input ocJfjOBHoro of the memory block, and the additional input is the sum The ora modulo two is connected to the corresponding output of the polynomial And error block.

The disadvantages of this device are the error corrections in the code combination are the complexity of the hardware implementation and low reliability.

The closest technical solution to the present invention is a device for detecting errors, comprising a serially connected input unit, a phasing unit, a gating unit, a first mismatch counter and a matching element, to the second input of which the output of the second mismatch counter is connected, the input of which is connected to the output of the gating unit sequentially connected integrator, an assembly element and a memory register, as well as an Error Detection block, the output of which is connected via an additional matching element n to the second input of the assembly element, the second output of the integrator through the decoder is connected to the second input of the additional element of the match, to the second

to the input of the decoder output is connected. an integrator, to the input of which the second output of the phasing unit is connected via a matching element, while the second output of the first mismatch counter is connected to the input of the error detection unit and the second input of the memory register 2. The disadvantages of the known device for detecting errors are low reliability due to the erroneous reception of the message in the absence of unreliable

0 characters (erasures) with distortion of the information part of the code combination; false rejection of the message due to the distortion of the check bits of the code combination with the correct

5 reception of the information part and the permissible amount of deletions.

The purpose of the invention is to increase credibility.

The goal is achieved by the fact that

0 a device for detecting errors, containing a serially connected input unit, a phasing unit, a gating unit, a unit, a first counter, mismatches, and a matching element,

5 to the second input of which is connected. the output of the second mismatch counter, the input of which is connected to the output of the gating unit, an integrator connected in series, an element

0 assemblies and a memory register, as well as an error detection block, a serially connected key, a combination sensor, a first modulo two adder, an I element, a second module 5 modulo two and a first switch, as well as a second switch and a prohibition element serially entered, the output of which is connected to the second input of the element

 assembly, to the third input of which the output of the error detection unit is connected to the input of which the output of the first switch is connected, the second input of which is combined with the second input of the memory register, the second

5 inputs of both adders modulo the bottom and connected to the second output of the first mismatch counter, the third input of the first switch is combined with the third input of the register of the register, the first input of the key, the first input of the second switch and the first output of the phasing unit the second switch is connected

5 to the second input element And, the output of the memory register is connected to the second input of the key, and the second output of the second switch is connected to the input of the integrator, and the output

0 of the first modulo adder

connected to the direct input of the prohibition element.

The drawing shows a structural electrical circuit device

5 for detecting errors.

The device for detecting errors contains an input unit 1, a phasing unit 2, a strobe unit 3, first and second mismatch counters 4 and 5, a match element 6, an error detection block 7, a memory register 8, an assembly element 9, an integrator 10, a combination sensor 11 , the first and second switches 12 and 13, the first and second adders 14 and 15 modulo two, the element And 16, the key 17, the element 18 of the ban.

The error detection device operates as follows.

The transmitted information is encoded with a redundant separable (pc) code, where n is the length of the code combination, k is the number of information bits. Test bits, the number of which is equal to nk, are transmitted after the information.

Binary signals of code combinations are fed in a sequential form, starting with information bits, from the input of the device for detecting errors to the input unit 1. In the input unit 1, the signals are converted to the corresponding type, match current and voltage with the input and arrive at the inputs of unit 2 and gate gate 3. Block 2 generates clock gate pulses that are applied to the clock input of gate gate 3, where code sequences are generated. In the mismatch counters 4 and 5, the code sequences of opposite polarities are analyzed, and the meaningful positions of the code combinations are formed at the information output of the counter 5. At the control outputs of counter 4 and 5, binary signals are generated which enter the coincidence element b.

From the information output of the mismatch counter 5, the code elements are sent to the 8-lam register for temporarily memorizing the primary part of the combination part, as well as to the error detection unit 7 through the switch 12, which is controlled. signal from the block 2 output.

If there are no mismatches at the output of the control outputs of both counters 4 and 5, at the output of the terminal 6, an impulse is generated indicating the presence of an invalid character (erasure). This pulse is fed to the input of the integrator 10, the input of which is connected to the output of the coincidence element 6 at the time of reception of information symbols in a code combination using the resolved signal from block 2 fed to switch 13.

If the number of invalid information elements exceeds the threshold value at the output of the integrator 10, an overflow signal appears, which is fed through the assembly element 9 to the fault input of the memory register 8. This signal completes the reception of the check bits of the code combination, the information in register 8 is erased, the device detects errors in the mode of receiving the next message, and the Repeat channel in the POC systems sends a reshoot signal to the retransmission of the rejected code.

If the invalid characters are missing in the information part or their number does not exceed the threshold value, the device continues to accept the check bits of the code combination. By a signal from the enable output of block 2, the input of switch 13 is disconnected from the input of the integrator of counter 10 and connected to one of the inputs of AND 16, and the output of switch 12 is disconnected from the information output of the mismatch counter 5 and connected to the output of the adder 15 modulo 2. In this case, the input of the memory register 8 is disabled, preventing the code combination check characters from being written to its bits, and KEY 17 opens, preparing data bits from the memory register 8 to the combination sensor 11. The device for detecting errors enters the mode of receiving the test part of the code, combinations.

The check bits coming from the output of the counter 5 mismatches are simultaneously fed to the input of the adder 14 modulo two, and through the adder 15 modulo two and the switch 13 to block 7, in which the code combination is analyzed for the presence or absence of distortions. At the same time, modulo two at the second input of the adder 14 synchronously with the elements outputted from the output of the mismatch counter 5, test symbols from the combination sensor 11 are received, formed by encoding the information part of the combination received and recorded in memory register 8.

The test symbols issued from the outputs of the mismatch counter 5 and the combination sensor 11 are bitwise compared to each other on the adder 14 modulo two. The result of the comparison is fed to the input of the element And 16 and to the prohibition of the input of the element 18 of the ban.

The other inputs of the elements through the switch 12 are given a signal from the output of the element 6 coincidence, the presence or absence of invalid characters (erasures). In the case of identity, compare the No. jx bits at the output of the adder 14 modulo two, there is no signal, significant bits from the output of the counter 5 mismatch through the adder 15 modulo two and the switch 13 are entered into block 7, If there is no detection of information from register 8 # 1 tee arrives at the exit. The device for detecting errors goes into the mode of receiving the next message. If the information part of the code combination is received correctly and correct, it is corrected, the device for error detection provides correction of the received significant bits at which the wiping / unreliable elements occur , the discrepancies detected by the counters 4 and 5 and the coincidence element 6. In the case of distortion of the test part of the code combination, modulo two of the output of the adder 14 generates a signal that goes to one of the inputs of the element 16, to the other input of which d is most likely a signal about the presence of an unreliable element. As a result, at the output of the element 16, the signal that arrives at one of the inputs of the adder 15 modulo two and the second input of the last is fed to the distorted check symbol of the code combination that is received from the communication channel. At the same time on the modulo 15 modulo two inverts the distorted bit. Thus, the inversion of the distorted element of the test part is carried out each time this situation occurs. In most cases, this will correspond to the correction of the mistakenly accepted combination. In case of mismatch of like bits and there are no invalid characters in places, these mismatches, the signal from the output of adder 14 modulo two through the open prohibition element 18 and / assembly element 9 rejects the bits of the code combination recorded in memory register 8. This is done to eliminate undetected errors resulting from the distortion of the information part and the absence of invalid characters in the process of receiving the message. The proposed device has a higher technical and economic efficiency compared to the known. The introduction of new elements and connections into it allows us to significantly increase the reliability of reception without significantly reducing the relative information transfer rate.

Claims (1)

ERROR DETECTING DEVICE, comprising in series connected input unit, phasing unit, strobe unit, first mismatch counter and sov- element. a fall, to the second input of which the output of the second mismatch counter is connected, the input of which is connected to the output of the gate block, an integrator, an assembly element and a memory register connected in series; as well as an error detection unit, characterized in that, in order to increase the reliability, a combination key, a combination sensor, a first adder modulo two, an element And, a second adder modulo two and a first switch, as well as a second switch in series, are introduced and a prohibition element, the output of which is connected to the second input of the assembly element, to the third input of which the output of the error detection unit is connected, to the input of which the output of the first switch is connected, the second input of which is combined with W eye input memory register, the second inputs of both adders modulo two and connected to the second output of the first counter mismatch, the third input of the first switch is integrated with the third input _Q memory register, a first input key, the first © input of the second switch and connected to the second output of the phasing unit, the first output of the second switch is connected to the second input of the And element, the output of the memory register is connected to the second input of the key, and the second output of the second switch is connected to the input of the integrator, and you the first adder modulo two is connected to the direct input of the prohibition element. ... SU_ _m , 1100746