SU1083406A1 - Device for generating alphanumeric and graphic image signals - Google Patents

Abstract

A DEVICE FOR THE FORMATION OF ALPHABET-DIGITAL AND GRAPHIC IMAGES, containing a synchronous generator, a block of address counters, the outputs of which are connected to the corresponding address outputs of the memory block, and a symbol generator, different in that, in order to simplify the device by reducing memory modules, in order to simplify the device by reducing the memory size of the memory modules, in order to simplify the device by reducing memory modules, in order to simplify the device by reducing memory settings. capabilities and improvement of the quality parameters of the generated images, the block of the change of the address is inserted in it, which is connected between the first output of the clock generator and the first and volts the inputs of the address counter block, the control signal generating unit, the recovery unit, the symbol reversal control unit, the color component generating unit and the digital-to-analog converter (D / A converter), while the information input of the control signal generating unit is connected to the output of the memory unit and the combined information the inputs of the block of the change of the address, the block of address counters and the recovery block; the input of the recovery unit, and the second output - with the control inputs of the block for changing the address and the address counters block, (L the first, second and third outputs of the recovery block are connected to the first inputs of the symbol reversal control block, the symbol generator and the signal generating unit of the color components, and the fourth output is to the additional information input of the control signal generation unit, the third co 4 output of the synchronous generator is connected to the synchronous input of the reversion control unit with characters, the output of which is connected in series with the symbol generator and the signal conditioning unit of the color components connected to the input of the DAC.

Description

The invention relates to television, in particular to the electronic synthesis of complex TV images 5 and may find application in the construction of a variety of alphanumeric and graphic displays, TV test images and tables in the transmission systems of fixed TV images when creating television cartoons and background images for gaming machines and simulators; in specialized devices for displaying information, in particular, when forming mnemonic diagrams and everywhere5 where it is necessary to create a complex television image, transmit it over a narrow-band communication channel, eliminating redundancy first, and recover in the simplest way or ensure reprogrammed image synthesis using the minimum memory size. Of particular importance is the invention when creating TV systems for mass information and reference services. Devices for the electronic generation of complex television images are known, based on analog, discrete and combo methods of formation of lj. However, these devices are designed to form specific images and therefore do not allow the formation of various images by changing programs. A significant reduction in the redundancy of television images is both done in digital systems, in which the television signal is subjected to a linear transformation. The original image is divided into zones, the calodes of which are described by a splinter matrix by elements 2. ,, „The disadvantages of devices that implement the principle of linear transformation include the considerable complexity of decoding. So, for example, applying the Fourier transform requires 4 multiplications and the same number of additions, the Hadamard transform requires 4 additions, and for calculating the Karhunen-Loeve-Pugachev transformation, approximately para arithmetic operations are required. The closest in technical essence to the present invention is a device for generating alphanumeric and graphic signals containing a synchronous generator, a block of address counters, the outputs of which are connected to the corresponding pagadti block address inputs and a symbol generator h. This device is difficult, because regardless of the complexity of the image signals, the entire memory takes part in the formation. The purpose of the invention is to simplify the device by reducing the memory size while maintaining the functional capabilities and improving the quality parameters of the generated images. The goal is achieved in that the device for alphanumeric and graphic signals containing the synchronization generator, the block of address counters, 1 which is connected to the corresponding address outputs of the memory block, and a symbol generator, an address reversal block is inserted, switched on between the first sync output The generator and the first and second inputs of the address counters block, the control signal generation block, the recovery block, the symbol reversal control block, the color component signal shaping unit and the digital-analog converter (D / A converter) are at the same time the information input of the control signal generation block with E; by the memory block stroke and the combined information inputs of the overhaul block a, 4pecas of the address counters block 5 and the recovery block, the sync input is connected to the second output of the sync generator} the first 2YOUT with control The main input of the recovery unit, and the second exit, with the control of the cadmium of the input unit and the block for changing the address and the block of address counters, the first second and third outputs of the recovery unit are connected to the first inputs of the symbol reversal control unit (symbol generator and color signal generator unit, and the fourth exit - to; additional information input of the control signal generation unit 5, the third output of the synchronous generator is connected to the synchronous input

3

the symbol reversal control unit, the output of which is connected through the serially connected symbol generator and the signal forming unit of the color components to the input of the DA11.

Fig. 1 shows the structural electrical circuit of the device for generating alphanumeric and graphic signals of their images; in fig. 2 is a structural electrical circuit for generating control signals; in fig. 3 - structural electrical diagrams of the block for blocking the change of address and block of address counters and their main connections with the prediction block; in fig. 4 table generated characters.

The device contains a synchronous generator 1, a block 2 of address counters consisting of the first and second address counters 2-1 and 2-2, a block 3 of memory and a generator of 4 characters, block 5 of the prohibition of changing the address consisting of parallel channels 5-M and 5-2, a control signal generation unit 6, a recovery unit 7, a symbol reversal control unit 8, a color component signal generating unit 9 and a DAC 10.

In this case, the control signal generation unit 6 comprises a pulse distributor 11, logic generation elements 12-20, a logic driver 21, a trigger 22, an inverter 23, an intermediate memory register 24.

Block 5 of the prohibition of changing the address contains two identical parallel channels 5-1 and 5-2, consisting of binary counters 25, logic cells 26-28 and triggers 29.

The device works as follows.

The memory unit 3 is intended for storing a television picture composition program consisting of codes, symbols, and control codes. It allows information to be stored between update cycles and output it in synchronization with a television scan. Depending on the nature of the use of the device, the memory may be made in the form of a memory device with an arbitrary selection of information (television displays and video terminals, mark-forming devices, etc.) or

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in the form of a permanent storage device-1 (generators of television test images and tables, specialized information display devices 5, etc.).

The amount of memory is determined by the number of familiarity and the size of the codes selected, which in this case reaches 7–8 bits. In the form of test images and tables, as well as when using the device as a TV, a specialized information display device, the memory block can be

c is designed as a reprogrammable or removable memory block. The rest of the storage unit is no different from the storage devices of modern alphanumeric displays.

The information to be displayed is arranged in the sequence shown in the table in FIG. 4. At the same time, each of the displayed characters corresponds to a certain number of bytes. The status byte, being distinguished from the remaining bytes by the presence of zero in the zero bit, indicates which of the next bytes should be read into the intermediate memory of the recovery unit. This indication is provided by writing a unit to bits 1-6. In this case, the corresponding symbol management (Fig. 4o), the repetition of the previous one (Fig. 45), Transition to a new color (Fig. 4b), Transition to a new symbol brightness (Fig.), Transition to a new background brightness ( Fig. 4e), as well as the Transition to a new symbol (Fig. 4e).

The parallel code from the output of the memory block 3 in the information acquisition mode is fed to the information input of the block 6. The block 6 is designed to extract the control symbols from the incoming array of information and form control symbols from them

0 signals, which are distribution pulses. They arrive at the control input of the recovery unit, indicating in which of the registers the next byte of information should be recorded. In addition, block 6 generates control signals, which, being fed to the inputs of block 2 of address counters 5, change the pattern of the TI and TI clock pulses. The control signal generation unit 6 (Fig. 2) is a digital device, the intermediate memory register 24 of which completes and stores the status byte. For this, the lower bit of the input signals is connected to the input of Ra

register entry decision. The distributor 11 pulses, made5 for example, in the form of a counter-decoder, with the help of logic gates AND alternately reads information from the bits of the register of the intermediate memory. The logical driver 215, consisting of logical elements of types AND and OR, produces the formation of pulses controlling the operation of the block of address counters. In addition, block 6 includes an RS flip-flop 225, which is triggered by a control pulse of the symbol. The transition to a new symbol and a reset are performed by the zero bit of the next status byte. The signal generated from element 20 (I) controls the operation of the pulse distributor by creating priority to the symbol. Switch to the new symbol. Elements 18 and 19, which are switching cells that are controlled by a pulse. Switching to the address provides switching of symbols. Switching to a new brightness of a bridge and Switching to a new brightness of a background in a necessary direction.

The recovery unit 7 is an intermediate memory device in which all the parameters S included in the control characters of this familiarity, as well as those that in the previous familiarity do not require changes, are memorized. The recovery unit is executed using two groups of memory registers. The information inputs of the first group of registers (five registers intended for receiving control characters are simultaneously given codes from the output of the block. At the same time, the recording of one or another control character in its register is provided by the control; they are enabled by the write enable signals from the output of the block 6. After all managers are received

ox, symbol luminance, background luminance, chroma and control. Exception Compose repetition codes, which are directly written to the block of address counters.

The block 2 of address counters is designed to form a complex sequence of clock pulses for starting the address counters. The program for submitting clock and start-up pulses to the outputs of the address counters is recorded in a permanent memory; its device (ROM) of the memory block and in the process of reading the information sent to the input of the block.

The program for managing address counters provides for the possibility of either skipping cycles or a leprechaun at a given address. The block of address counters in this case provides an easy loop skip. Indeed, if a group of adjacent characters in the imaged image does not require any transition in the process of combining the two, which usually occurs 3 processes of displaying identical characters with the same-f characteristic and ifBeTHocTHj, naturally; In the process of image synthesis, it is not necessary to change the codes of the generated images, and hence the addresses of these codes. Therefore, it is enough to miss the unsuitable number of cycles by triggering the start impulses given to the input address counters. Such an operation in the dscresk counter block is implemented as follows. In normal mode,; t S, with alternate cleaning from the cells of the unit. clock pulses familiarity horizontal di1; retiring TIs from the output of synchro-generator 1 (Fig 3) are fed through logic cells 27 and 28 (respectively AND to OR) to the counting input of the first address counter 2-1, which forms the characters, and overwrites all the characters into the second one at the same time pear registers. Thus, if in the first group of registers the change signals are received (the transition of the parameters of the generated images, then in the second group of registers codes of all the image parameters for this familiarity are formed, namely the codes its address is +1. The second input of the logic cell 27 is fed 1, removed from the direct output of the RS flip-flop 29. This signal is a strobe for the pulses THj {. When reading the information, the control character (byte) Repeats the previous one, indicating how many times the previous one should be repeated, is recorded in a binary counter 25. A logic cell 26 connected to the inverse outputs of a binary counter generates pulses, the logical function of which F abJd corresponds to the appearance of pulses in the zero state of a binary counter. Therefore, when writing a byte, the previous one in the binary counter 25 is recorded simultaneously with the record setting the RS flip-flop to the state O by applying a write pulse to the input R. From this moment on, the TIH pulses stop on the counting input of the first address counter 2-1 until co of a binary counter 25 in subtractor mode becomes equal .About. When this impulse from the output of logic cell 26 sets the RS-flip-flop to state 1 and the clock pulses TI) will begin to arrive at the counting input of the address counter 2-1. Thus, at the output of logic cell 27, it forms with the impulse of advancing the address to the next byte of states at each familiarity, while the impulses of advancing the address to the remaining bytes of this familiarity are formed by the logical driver 21 of block 6 and fed to the second input of the logical cell 28 (OR). Thus, regardless of the presence of the symbol Repeating the previous one, all pulses necessary for interrogating the memory of this familiarity are sent to the address counter. It should be added that the block for blocking the change of the address along the vertical does not have any fundamental differences, however, it does not require the OR cell, similarly to the logical cell 28. The address counters of block 2 (fig. Are intended to form current addresses to get information from the memory block. They provide as single incrementing the address on the X and Y axes in the counting mode, and going to the specified address 6 "practically to any familiarity of the address field. The address counters consist of two binary counters to ensure separate sampling of data on horizontals and verticals, in addition to the counting input, have parallel information recording inputs and are no different from known microelectronic circuits, the sync generator is a device designed to generate the necessary clock and sync pulses. The symbol reversal control unit 8 is a device that allows you to commands recorded in the Byte Symbol control (FIG. 4a), to provide a reversal (symmetric display) of the symbol horizontally, vertically or horizontally Ntali and verticals simultaneously. The use of such a technique allows in some cases to reduce the number of characters written to the symbol generator by 4 times. For example, when forming circular shapes on a TV raster, it’s enough to write characters in the symbol generator that describe only one quarter of the shape being formed. The remaining parts, which are congruent, mirror-symmetrical figures, can be obtained by applying reversal. Block 8 consists of code inversion nodes. For example, reversing the characters horizontally with the matrix method of forming symbols can be achieved by changing the shift direction (left to right) of the shift register used for parallel-serial conversion of data read from the character generator ROM matrix. Reversal of characters vertically in the matrix method of forming characters is easy to achieve by inverting the data sample codes when reading from the matrix of the character generator ROM. The described operations are widely used in various automation devices and are described fully enough in l, The 4 character generator is designed to form various characters (characters ) in the limit of the familiarity. Symbol Generator9

Cards can be conditionally divided into standard generators (letters, numbers, punctuation marks, mathematical signs, etc.) of symbols and non-standard symbols (symbols of arbitrary shape, which are inherent only in this formed image). The principles of construction of these generators are absolutely identical, however, if the generator of standard symbols is made on the basis of ROM, then the generator of non-standard symbols is based on RAM. Such an approach makes it possible to obtain characters of practically any configuration, since in each individual case any set (alphabet) of characters can be written into the memory of the generator of non-standard characters. Using the generator of non-standard characters, you can also form the hieroglyphs of the Japanese and Chinese alphabets.

The color component signal generating unit 9 is designed to generate the color component signals of the image Fj, FQ, Fg, represented in the form of a parallel binary code. Since the input of block 9 receives the binary signals of the generated symbols C and C, the binary signals of chromaticity B, R (s G and Bf, Rq, 5 Cf, the binary signals of the character's width ad - .., and the binary signals of the background brightness bg - bj, ., it is not difficult to form binary variables for the Fg signal using logic cells.

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Finally, the formation of the color components is carried out with the help of the CLA 10. In this case,

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The analysis of the technological efficiency of the proposed device, 5 compared to the known, shows that it allows the formation of images of practically any configuration while reducing the memory size and simplifying the device.

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Claims (1)

DEVICE FOR FORMING ALPHABET-DIGITAL SIGNALS AND GRAPHIC IMAGES, containing a sync generator, a block of address counters, the outputs of which are connected to the corresponding address outputs of the memory block, and a symbol generator, characterized in that, in order to simplify the device by reducing the amount of memory while maintaining functionality and improving the quality parameters of the generated images, he entered the block prohibition of changing the address, included between the first output of the clock and the first and second inputs of the block address counters, the formation of the control signals, a recovery unit, a symbol reversing control unit, a color component signal generating unit and a digital-to-analog converter (DAC), while the information input of the control signal generating unit is connected to the output of the memory unit and the combined information inputs of the address change prohibition block, address counter block, and block recovery, the sync input is connected to the second output of the sync generator, the first output is connected to the control input of the recovery unit, and the second output is connected to the control inputs of the unit To prohibit changing the address and address counter block, the first, second, and third outputs of the recovery block are connected to the first inputs of the symbol reversing control block, symbol generator, and color component signal generation block, respectively, and the fourth output to the additional information input of the control signal generating block, third the output of the clock is connected to the clock input of the symbol reversing control unit, the output of which is through series-connected symbol generator and the block of Signals of color components are connected to the input of the DAC.