SU1354182A1 - Information displaying device - Google Patents

Abstract

The invention relates to computing and can be used. It is called for when developing universal devices for displaying symbolic and graphical information. The purpose of the invention is to expand the field of application of the device by allowing the display of information with operatively variable raster parameters. (L 00 JV 00 ito

Description

135A

The goal is achieved by introducing into the bus driver unit 16, control unit 9, decoder 23, subtracting counter 22 of trigger 7, block 10 of program memory n symbol graphics, block 11 of symbol code memory and 1 multiplexer 6 and corresponding functional links, B device / device it is possible to change the decomposition matrix of the symbol, that su

The invention relates to computing technology and the markets to be used in the development of universal devices for displaying sign and graphic information.

The purpose of the invention is to expand the field of application of the device by the ability to display information with operatively variable raster parameters.

Figure 1 shows the functional diagram of the device; figure 2 shows the time diagrams of the device's rabota.

The device contains a clock generator 1, a binary counter - a frequency divider, a counter of 3 characters, lines and rows, a video memory block 4, a shift register 5, a multiplexer 6, a trigger 7 (D-flip-flop), an address trunk 8., a control block 9 ( microprocessor), block 10 of program memory and graphics characters, block II, pa-M5iTH character codes, address selector 12, And elements 13 and 14., bus 15 records of the national driver 16, highway 17 danzh, registers 18 and 19e I1inu 20 readiness, synchronization unit 21, subtractive counter 22, decoder 23, digital-to-analog converter (DAC) 24, counter 25 lines, DPL 26, source 27 of the reference voltage.

The clock generator 1 generates rectangular pulses with the following frequency F () Hz, where No. is the number of cells of memory block 4, zeo-information, M is the number of information bits in the word of block 4 of video memory non-path information; 1 "video signal formation (shift register size 5 shift), K82

It significantly increases the flexibility of the device (allows displaying letters of various alphabets and hieroglyphs), improves ergonomic characteristics, and the possibility of programmatically changing raster parameters & raster allows using the device with almost any monitors. Using a raster scan, and ostsoshhograf, 2 Il.

five

five

maximum frame rate or half frame.

Multiplier 2 is present in the formula for the reason that the cycle for accessing blocks 4 consists of two cycles: the cycle of reading information into the shift register 5 and the cycle of transmitting or receiving information from (or c) 1 of control block 9.

Increasing the clock frequency somewhat increases the requirement for the parameters of individual units, but at the same time guarantees high image quality, since the process of information exchange with the microprocessor 9 does not affect the information display process.

The size of the counter-divider 2 frequency, made in the form of a meter, and the volume of the pag-pin unit 21 depend on the type of video memory used,

The counter size of 3 characters, lines and rows is determined as the logarithm of the base two of the number of cells in block 4, the required volume of which is calculated by the formula

NE (a + u-c + d) (e + f + g + j),

N is the number of memory cells of block 4;

Cjd-- the number of cells of block 4 allocated for the forging of a horizontal sync pulse of maximum duration, a left blanking pulse of a maximum duration, a right blanking pulse of the maximal long-IT line of the video signal, respectively

313

(thus, the sum of a, b, c, d is the maximum number of cells of block 4 allotted to form a line of video signal, synchronizing and blanking line pulses);

e - the number of working lines of the monitor with the maximum number of working lines;

f is the number of lines used to form the location of the lower working line on the monitor screen (maximum);

g is the number of lines used to delay the formation of the image to exclude non-linearity of the frame scanner (maximum); j is the number of lines used to form a frame sync pulse. The shift register size 5 is chosen such that, in sum, with the register size 19, the microprocessor 9 turns out. The register resolution 19 is equal to the integer N1§2 (K + 2 ), where K is the number of necessary gradations of luminance, the term 2 reserves two levels for the formation of synchronizing and blanking pulses (N must be increased to the nearest integer number). The sampling rate of the DAC 24 video signal is (K + 2), where K is the number of luminance gradations.

The descrambler 23 selects one value from (K + 2). The preset number of the subtracting counter 22 is 1, and the condition L a must be fulfilled, where a is the number of cells 1 of block 4 allocated for forming the horizontal sync pulse of maximum duration.

The counter width of 25 rows is N iogi (e + f + g + j) (N must be increased to the nearest whole number, ae, f, g, j are defined above),

The number of discretizations of the D / A converter 26 (vertical deviation) must be equal to the sum e, f, g, j. The bit size of register 18 (data) is equal to the bit width of microprocessor 9 and block 4.

The operation of the device can be divided into stages: setting the operation mode, forming a raster and displaying information.

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When the power is turned on, microprocessor 9 starts executing an initialization program, reading command codes from block 10. Microprocessor 9, under the control of an initialization program, polls the state of switches (not shown) or transitions to standard operation mode settings. Setting the standard operation mode or setting the operation mode after analyzing the state of the mode switches includes setting the raster parameters (a, b, c, d, e, f, g, j) and stating the status of the status register (its role can be one of the microprocessor general registers or one of the RAM cells (which may be part of the microprocessor or connected to it in the usual way and therefore not shown).

The status register can have the following fields: a luminance code field and a display mode feature field (positive / negative, blinking, color, decomposition matrix code, graphic display code, etc.). After setting the operation mode, the microprocessor 9 switches to the raster generation program, which is accomplished by filling the block 4 with the program stored in block 10, the type of which depends, on the raster parameters. and the state register.

The information is recorded in block 4 as follows.

The microprocessor 9 exposes the address to the address highway 8, and the data highway 17 provides information intended for dp entries. The address selector 12, when the address of the video information memory block 4 coincides with the address set on address highway 8, generates a selection signal, which from the output of the address selector 12 enters the inputs of elements 13 and 14, thereby allowing the signal to pass through the second input.

The microprocessor 9 after the exhibition of the address and data transfers the write bus 15 to the active state, thus giving a write command that passes through the AND 13 element and from its output goes to the D input of the trigger 7 and switches the bus driver 16 to the information transfer mode line 17 of the data to the inputs of block 4 through the time determined by the frequency ta.

generator 1, bit

divider-divider 2, with the information wired in block 21, and the moment of amplification with respect to the state of quadrant-divider 2. The synchronization signal from the output 28 of the block 21 enters the trigger input 7 of the trigger 7 and the write signal from the output of the element And 13 is recorded in the trigger its output goes to one of the inputs of the multiplexer 6.

The signal from the output 28 of the block 21 switches the multiplexer b to thereby connects the address line 8 to the inputs of the address of the block 4. In the case of using dynamic memory with the built-in address register and multiplex transmission of the row and column select bits, the signal from the output 29 of the block 21 will switch the address and communication with block 4 will synchronize this switch.

 Simultaneously with the switching of the address inputs of the block 4 from the outputs of the counter 3 to the address highway 8, the output of the trigger 7 will be connected to the recording input of block 4, the C command will go to block 4 and a write cycle will be performed.

When generating synchronization signals (personnel (XSI) and lowercase (FID)), there are several ways to fill in block 4. In one of them, the microprocessor 9, according to the program stored in block 10, enters the first and 4 cells of the block 4 the sweeps of which, when scanned to the input of control register 19, contain a sync pulse code decoded by decoder 23, and a log, l, is written to the remaining bits. The following (b + c + d) cells are entered in the information corresponding to the accumulative pulse width (the upper bits go to register 19) and the frame picture (log, l or log, o). Thus, the first line of the image frame is formed. The process is repeated as many times as there are lines to form an image frame.

Then, the sync pulse code is written to the next cells and the code of the blocking pulse is recorded only in the b cells. In the following cells, a space code is recorded (the code corresponds to a white fenny, if the background is white, and black level, if the background is black,

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respectively log. 1 or log. About in the remaining bits). In the next d cells the blocking pulse code is entered. In this way, one active line is formed to display the video information. The process is repeated programmatically as many times as necessary to form active lines.

Then the process of forming is repeated.

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frame rows so many times that the working field is in the center of the monitor screen or on the linear portions of an oscilloscope frame scanner. 15

The sync pulse is similar to the process of creating a FID, but its code is written in a much larger number of cells.

At this point, the program stage of the formation of the raster is completed, at the outputs 30 (X), 31 (Y), 32 (Z) and 33 (XI) the control signals and

2 The device is ready to display information.

Time diagram 34 (Fig. 2.) shows a periodic sequence of pulses produced by generator 1. Charts 35-38 are the states of the counter-divider 2 outputs (implemented as a subtractor), timing diagrams are shown for the preset number P ,,,

Eight microprocessor 9,

 two-bit DAC 24, two-bit register 19 and six-bit shift register 5 implement seven levels of brightness (two bits provide four combinations and dependence on the signal level from the output of shift register 5, tvc you can get only eight levels5 but the first level is used for display cpumpumps, and seven to display the amplitude of the video signal of the image).

Counter-divider 2 provides twelve states ™, which ensures the formation of all the control signals from the output of block 21 according to the required diagrams (Fig. 2, diagram 39). Diagrams 40-44 are the states of the outputs 45-47, 29, and 28 of block 21, respectively. Diagram 48 is the switching time of the 1-Gultiplexer B output (for simplicity, the diagram is shown without taking into account delays relative to the splitter 2 counter), Diagram 49 is the the output of block 4, Diagrams1

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They are given the sampling time from block 4, which is important for synchronization of writing to registers 19, 5 and 18 by signals from outputs 45 and 46 of block 21.

The counter-divider 2 on the leading edge of the clock signals from the output of generator 1 changes its state by enumerating combinations at the address inputs of block 21. At state 1, the codes 45-47 and 29 of block 21 do not select cells 4 (the process is in progress) Yes, the output 28 is in the state O, which corresponds to the state of multiplexer 6, at which the address inputs of block 4 are connected to the outputs of counter 3. Upon completion of state 1, the signal at output 29 of block 21 will change the level (from log 1 to log. O) and the address of the counter 3 state (row address) is fixed to the address The common register of block 4 (the dynamic memory row is sampled). The same signal goes to the lower bit of the control input of the multiplexer 6 and switches the address inputs of the memory block to the outputs of the counter 3 to sample the columns.

In the counter-split state 2, outputs 45, 46, 29 and 28 of block 21 remain the same and a loan signal is generated (not shown in the diagram), which is preset to state 44 (Fig. 2, in which the output 47 of block 21 will change the state to the log. About, the state of counter 3, determining the column address in the block 4 address register, will be fixed, and the dynamic video memory block will be fully sampled (the output drivers will open (not shown) and after will go to the output of the block 4) In the state 44 did not occur It is possible to change the state of outputs 45-47, 29, and 28 of block 21, and only at the end of state 43 (Fig. 2) will output 45 of block 21 change from state of log O to log state 1, by recording information In register 19 and switching the shift register 5 to parallel reception of information, and using the next synchronization signal from the low-order output of the counter-divider 2, information is recorded in the shift register 5.

The signal from the output 45 of the block 21 is also fed to the counting input of the counter 22

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when forming the sync pulse. The preset number of the counter 22 is such that during the formation of the FID, the counter 22 does not have time to generate a loan impulse (no XI is generated), the reset pulse of the counter is 25 lines and the lines are counted. The counter 25 changes its state in line sync pulses from the output of the decoder 23, the DAC 26 forms a stepped voltage. nne.

At the end of state 43 (FIG. 2), the signals from outputs 29 and 28 of block 21 will be switched to a state log. l and multiplexer 6 will switch the address outputs and the write input of block 4, respectively, to address line 8 and the trigger output 7, and the signal from output 29 disables the selection of rows of block 4. In addition, changing the state of output 28 of block 2 implies, ( increment counter 3 and record the write signal to trigger 7, if it was present at its input.

In state 42, the control signals do not change, and at the end of state 41, the signal from output 45 of block 21 (control of parallel reception of register 5, shift) register 5 by pulses from the output of the low-order counter-divider 2 will begin to advance the video information to the DAC input 24, which, depending on the control code from the output of the register 19, will begin to form a video signal of a certain level.

At the end of state 41, output 47 of the dynamic memory column is sampled and the recovery process of block 4 begins (its outputs will go to state 49, figure 2). At the end of the state 40 of the splitter 2 counter, the row sampling signal (output 29: block 21) generates the row address read from the address highway 8, switches the address inputs of block 4 to the address busses of the address 8 defining the column address.

At the end of state 39, the column sampling signal (output 47 of block 21) generates the address of the column, block 4, depending on the state of the signal at the recording input, which is currently connected to the output of trigger 7, is working or in the mode of recording information from the data highway 17 which, through the bus driver 16, is supplied to the data inputs of block 4 via a signal from the output of element I 13, or in read mode. If there is no recording signal, the driver 16 connects the outputs of the register 18 to the highway 17.

States 38 and 37 are similar to states 44 and 43 (Fig. 2) with the difference that at this time the address register of block 4 stores the state necessary1) GC bits of the address highway 8.

When the signal log. 1 from the output 46 of the block 21, the information is written into the register 18 (via the element 14, if there was a call of the transmitter 9, i.e. if the address selector 12 was activated). The same signal will be sent to the readiness bus 20, which corresponds to a message to the microprocessor 9 about the TOMf that the information has expired on the data buses or that the cycle has been completed.

When the signal line selection log. 1 (output 29 of block 21), preparation of the dynamic to us for the next cycle begins, and in the state of output 28 of block 21, the address inputs of block 4 are connected to the outputs of counter 3. Signal selection of the columns at the end of state 35 (Fig. 2 ) the block 4 prespends are not in status. 36 and the microprocessor 9 cycle will end. Counter divider 2 will not trade into state 34 and the whole process will be repeated.

In this way, sequential output of information from each cell of block 4 is performed, information on the progress of the utchravlen is recorded in register i for each selected word, its information (6 bits), and conversion using the register: and the DAC 24 to a serial signal whose amplitude depends From register state 19,

Decoder 23 Constructed decodes a code in which the amplitude of the signal from the output of CLP 24 corresponds to the amplitude of syncro-tu.-Gos. The output signal of the decoder 23 can be used as an AUX in monitors with a separate AOS input or as an external synchronization signal 1formatsii on the axis of shlografe.

The counter 22 performs the subtraction only in cases where despatcher 1 defines the pulse sig-per code and a signal with the amplitude of the sync pulse is generated at the output of the DAC 24. If the number of counter preset 22 is greater than mac

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the maximum number of cells of block 4 assigned to form the FID, the loan signal from the counter 22 occurs only when the XI of their block 4 is read, i.e. counter 22 performs the functions of a time selector, which modifies the XI, which is used in monitors with a separate input XSI.

The loan signal from the output of counter 22 zeroes the counter 25 and stops the formation of step voltage at the output of the DAC 26. The step period. The voltage at the output of the DAC 26 is equal to the period of the frame frequency, and this signal can be used as a signal of vertical deviation when the information is sent to an oscilloscope.

In any cell of the block, 4, you can save- | Sat arbitrary information. Since the two high-order bits define the luminance code, six marshins are displayed as part of a line on the screen, it is possible to display both alphanumeric and 5 graphical information.

Display of alphanumeric information is carried out by entering into the defined cells of block 4 information corresponding to the graph of the symbol in a certain decomposition matrix for decomposition of the Russian and Latin alphabets more often use the matrix 5x7 or 7x9, and hieroglyphs 32x32). In some cases, to break up the written and lowercase bounds; GKB use 7x9 and 5x7 matrices, which significantly increases the flexibility of the device (allows you to display letters of different alphabets for hieroglyphs), improves ergonomic characteristics.

In a preprogrammed device, the process of simulating a graphics of a simzola is implemented using a microprocessor 9 but a program j-fMB stored in this block from the block 11 the code of the current symbol intended for dp display,

Shzhroprocessor 9 analyzes the state of the state register (not shown) determines the decomposition matrix and display mode (positive, negative, blinking, etc.) s reads from the special area of block 10, depending on the code "ashes of words”

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the first line of the graphics of the symbol, and switches it to block 4., flowed the second line, etc. as many paSf as the number of rows in the symbol decomposition matrix.

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Depending on the output mode, the read information is written, in block 4, in direct or inverse form, which corresponds to the display mode in positive or negative. If a 5x7 decomposition matrix is used, five bits of the string are used to output the character, and one to implement a space. If the number of columns in the decomposition matrix is more than six bits, each character string can be read in several cycles. Thus, it is possible to display symbols in different modes with different decomposition matrices.

Since the character generation process is implemented in software, to generate a symbol with a different graphic or with another decomposition matrix, it is enough to call another program or change its input parameters. This capability allows for prompt changes in the used alphabet and graphics of symbols and uses one device to output both alphanumeric and graphical information.

The proposed device generates a full video signal (the signal from the output of the DAC 24, which contains the video signal, DDS and XI), which can be fed to the video input of the television receiver for display. At the outputs of the decoder 23 and the counter 22, the FID and the FID are formed, which makes it possible to use this device for working with monitors that have separate inputs to the FID and the FID and which do not have a selection circuit for these pulses from the video signal. The presence of a step signal with a period of the frame frequency from the output of the DAC 26 and separate signals of the horizontal frequency and the video signal, when connected, corresponds to the inputs of vertical 5: clone, external synchronization and brightness control, allows the device to display information on the oscilloscope .

formula of invention

A device for displaying information comprising a clock generator, the output of which is connected to the input of a binary counter-frequency divider counter-,

a sign of characters, lines and rows, a video memory block whose outputs are connected to the information inputs of the shift register, the first and second digits

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analog converters, two registers, row counter, two I elements, an address selector, a reference voltage input of the second digital-analog converter, connected to a source: a reference voltage, trigger, and a synchronization unit, so as to extend the field of application devices by providing the possibility of displaying information with operatively changing raster parameters, it contains a bus driver, a control unit, a decoder, a subtracting counter, a program memory block and symbol graphics, a block there are several character codes and a multiplexer, informational inputs of the first group of which with the outputs of the counter of characters, lines and rows, address input - with the output of the trigger, address inputs of the group - with the outputs of the first group of the control unit, connected to the address inputs of the memory blocks These programs and graphics of symbols and codes of symbols, the outputs of the counter of signs, lines and rows are connected to the information inputs of the multiplexer, the first output of the synchronization block is connected to the synchronous input of the first register, the control input of the shift register and the counting input m subtractive counter, the second output - with the first input of the first element And, the second input of which and the first input of the second element And connected to the output of the address selector, the second input of the second element And connected to the output of the first element And connected to the synchronous input of the second register, controls the inputs control block and program memory blocks and graphics of symbols and character codes, the third output of the synchronization block is connected to the sample input column of the video information storage block, the fourth output is connected to the sample input line of the video memory block Formations and the first control input of the multiplexer, five output - with the second control input of the multiplexer, the counting input of the counter of characters, lines and rows and the trigger trigger input, the information input of the trigger connected to the control. the input of the bus driver, the information inputs of the first group of which are connected to the outputs of the program memory and graphics of the characters of the control unit and the memory of the character codes 13 13

The outputs, readiness outputs of the control unit and program memories and graphics of symbols and character codes are connected to the second input of the second element, and the outputs of the shift register are connected to information inputs of the second group of the bus driver, the outputs of which are connected to the information inputs of the video memory block, the outputs of which connected to the information inputs of the first and second registers; the address inputs and the recording input of the video memory block are connected to the corresponding multiplexer outputs; the output of the lower the bit of the binary counter-frequency divider is connected to the synchronous input of the shift register and the low-order bit of the address input of the synchronization unit, the other address inputs of which are connected to the corresponding outputs of the binary

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the frequency divider counter, the outputs of the first register are connected to the decoder inputs and the information inputs of the first digital-to-analog converter, the input voltage of which is connected to the output of the shift register, and its output is the device video output, the decoder output is the device's horizontal sync pulse output and is connected with a counting input of a row counter and an installation input of a subtracting counter, the output of which is the output of the device clock sync pulses and connected to the reset input of the counter st ok, the outputs of which are connected to the data inputs of the second digital-analog converter, the output - which is the output signal of the vertical beam deflection device.

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Editor P.Geershi

Compiled by I.Zaginayko Tehred M. Iodannch

Order 5694/43 Circulation 671 Subscription

VNIIGGI USSR State Committee

on affairs of inventions and discoveries 113035, Moscow, Zh-ZZ, Raushsk Ha6.j d. 4/5

Production and printing company, Uzhgorodr st. Project, 4

Proofreader S. Shekmar

Claims (1)

Claim A device for displaying information containing a clock, the output of which is connected to the input of a binary counter-frequency divider, a counter of characters, lines and rows, a video information memory block, the outputs of which are connected to the information inputs of the shift register, the first and second digits of 1354182 analogue converters, two registers, a counter lines, two AND elements, an address selector, the voltage input of the second digital-to-analog converter is connected to the voltage reference source, a trigger and a synchronization unit, which differ That, in order to expand the field of application of the device by allowing the display to prompt the raster variable parameters, it comprises a bus driver, a control unit. a decoder, a subtracting counter, a program memory block and symbol graphics, a memory block of symbol codes and a multiplexer, the information inputs of the first group of which are connected to the outputs of the counter of characters, lines and rows, the address input with the trigger output, the address inputs of the group with the outputs of the first group of the block control, connected to the address inputs of the memory blocks of programs and graphics of characters and character codes, the outputs of the counter of characters, lines and rows are connected to the information inputs of the multiplexer, the first output of the synchronization unit is inen with the first register sync input controlling the shift register input and the counting input of the subtracting counter, the second output is with the first input of the first element And, the second input of which is 35 and the first input of the second element And are connected to the output of the address selector, the second input of the second element And is connected to the output of the first AND element, connected to the sync input of the second redistributed histogram, the control inputs of the control unit and the program memory blocks and graphics of symbols and symbol codes, the third output of the synchronization block is connected to the sample input of the column block and video information memory ₄₅ , the fourth output — with the input of a row sample of the video information memory block and the first control input of the multiplexer, the fifth output with the second control input of the multiplexer, the counting input of the character counter, lines and rows, and the trigger sync input, the information input of the trigger is connected to the output of the second element And connected to the manager 55 to the input of the bus driver, the information inputs of the first group of which are connected to the outputs of the program memory block and character graphics, control unit and memory block of codes 13, outputs of the readiness of the control unit and program memory blocks and graphics of symbols and symbol codes are connected to the second input of the second element AND, the outputs of the shift register are connected to the information inputs of the second group of the bus driver, the outputs of which are connected to the information inputs of the video memory unit, the outputs of which are connected with the information inputs of the first and second registers, the address inputs and the recording input of the video memory block are connected to the corresponding outputs of the multiplexer, the output of the lowest time a row of a binary counter-frequency divider is connected to a shift register sync input and a low-order bit of the address input of the synchronization block, the other ₂ θ addresses of which are connected to the corresponding outputs of the binary counter-frequency divider, the outputs of the first register are connected to the inputs of the decoder and the information inputs of the first digital-to-analog converter the input of the reference voltage of which is connected to the output of the shift register, and its output is the video output of the device, the decoder output is the output of lowercase sync device pulses and is connected to the counting input of the line counter and the setting input of the subtracting counter, the output of which is the output of the frame clock of the device and connected to the reset input of the line counter, the outputs of which are connected to the information inputs of the second digital-to-analog converter, the output of which is the output of the device vertical deviation signal. Memory W J i Figure 2