SU1057958A1 - Device for primary processing of seismic information - Google Patents

Description

105 2. The device of claim 1, wherein the control unit contains an address counter, the output of which is the first output of the block, and the input is the input of the block and is connected to the input of the first delay element, the output of which is 8 the second output of the block and the input of the second delay element, which is connected to the input of the third delay element and to the third output of the block, the output of the third delay element is connected to the fourth output of the block.

The invention relates to seismic analysis and can be used in the processing of seismic signals and in hydroacoustics. A specific feature of the recordings of recorded seismic signals is a decrease in the visible frequency and spectral band as the recording time increases, which is associated with selective non-linear absorption of seismic waves in the earth formation under study. A number of methods and devices are known that use time-varying filtering as a means of increasing the signal-to-noise ratio in the preprocessing stage. A device is known, tl J, in which the recording of seysk cic signals. The digitized ones are broken down into a series of temporal overlapping intervals for which the filter operators calculate the best to isolate the signal component within the centers of each interval. The non-overlapping seismic recording sections at the output of the filters form part of the filtered recording. Overlapping areas of neighboring intervals at the output of the sums filters with weights linearly varying from one to zero in accordance with the expression 2r (t) ipt; Se. where S (i) - The value of the output recording of seismic signals on the overlap section; V (t) .Se seismic records on the overlap section from the left and right interval filter outputs; t., i - initial (Left and second consecutive time counts of the overlapping section. The device has the disadvantage device for primary seismic information, containing serially connected seismic source, narrow-band filters, amplitude: limiters, band-pass filters, sums Ator and recorder. I The seismic signal source is connected to U-bandpass filters to separate the frequency components of the signal, the outputs of these filters with amplitude limiters to limit the amplitudes of the selected frequency components one by one, the amplitude limiters are connected to the inputs of the bandpass filters. The bandpass filters of the adder are connected to the recorder. The number of narrowband filters, amplitude limiters and bandpass filters corresponds to the number of frequency filters 101 x for which the signal is laid out. The signal being processed from the signal source is fed to the parallel inputs of narrow-band filters. The number of these filters is determined by the frequency range of the seismic signals and the frequency decomposition chosen by the frequency difference. The selected frequency components, which have different amplitudes, arrive at amplitude limiters, where the amplitudes of the frequency components are limited to the same level. The amplitude-equalized frequency components are applied to band-pass filters, where high-frequency filters are filtered out, spectral components due to the amplitude-limiting procedure. After the bandpass filters, signals will be sent to the adder, and the summed frequency components will be sent to the recorder, i.e. using bandpass filters filter out high-frequency components arising due to amplitude constraints. C23 Device drawback is the presence of a large number (at least four narrow-band filters and, accordingly, at least four amplitude stops and the same number of band-pass filters. Such an abundance of details of the same type makes the circuit cumbersome. . The closest to the proposed technical entity is a device containing a memory block of a code sequence of seismic signals. c, the memory block of the code table of the distribution of the fundamental frequencies of the seismic signals from the time of their recording, the computing block with the additional memory of the processing programs, the digital-to-analog output block, the band-pass filter The alignment process of the frequency spectrum of the seismic signals in the device includes non-linear time-scale digital conversion seismic signal recordings, performed by a computing device, by programs embedded in its memory. With a non-linear time-scale transform, the original seismic signal record. (with a known distribution of their main-basis oscillation periods), is deformed by means of a compression-growth operation 1, so that seismic signals are obtained at which the oscillation periods are close to each other. Further, a sequence of requests that follow at regular intervals, samples of signals from the memory block, are fed to the input of a digital-to-analog converter (DAC), and then to a band-pass filter, from which the recording of seismic signals in a nonlinear time scale is fed to the input of the image builder 3 J. 1 58 Disadvantage of the device is the presence of a computing unit (computer /, which increases the cost of the device, and the principle of time-scale conversion by this method slows down the processing. Another disadvantage of the device is that filtering is variable in time as a means of increasing the signal / noise ratio Often, at the initial or intermediate stages of digital processing, there is an analog representation of the signal, with a non-linear time scale, which does not allow subsequent processing by standard methods and requires, at a minimum, an inverse non-linear time-scale conversion operation. The purpose of the invention is to simplify the device and increase its speed while maintaining the original view of the seismic signals. To achieve the goal of the device for primary o6pa6otKH seismic information containing the control unit, the first and second outputs of which connected to the first and second inputs of the first and second memory blocks, respectively, a digital-to-analog converter, whose information input is connected to the output of the first the memory unit, the control input to the third output of the control unit, and the output to the input of the bandpass filter, an OR element, an analog-to-digital converter, a register, and a code-interval converter, the input of which is connected to the output of the second memory block, and the output through the OR element - with the input of the control unit, the fourth output of which is connected to the third input of the first memory block, the information input of the analog-digital converter connected to the output of the bandpass filter, the control input - with the third output of the control unit neither, and the output through the register, with the fourth input of the first memory block. The control unit contains an address estimator, the output of which is the first output of the block, and the input is the input of the block and is connected to the input of the first delay element, and the output of which is the second output of the block and the input of the second delay element that is connected to the input of the third the delay element and the third output of the block, the output of the third delay element connected to the fourth output of the block. Figure 1 presents the block diagram of the device; 2 is a control block diagram. The device contains a control unit 1, a first memory block 2, a second memory block 3, a digital-analog converter k, a band-pass filter 5, an OR 6 element, an analog-to-digital converter 7, a register 8, a code-interval converter 9. Control unit 1 (FIG. 2 contains an address with 4 detector 10, a first delay element, a second delay element 12 a third delay element 13, In the prototype of the device, a nine-channel digital-to-analog converter with an R-2R matrix has a settling time of less than 2 µs; This parallel-to-serial ADC is implemented according to a cadre scheme on integrated circuits and discrete elements with a conversion time of less than 3 MKS. The 9x2 A memory module is assembled on the basis of RAM (565RU2) with a write cycle time (read less than 2 µs. Digital logic nodeson the TTL IC (155-seri). The device works as follows. At the beginning, block 2 is loaded with seismic information (trace), presented in digitized form, and the initial (small) addresses of block 2 correspond to a short recording time. the code sequence (table) representing the actual distribution of the fundamental frequencies of the useful waves as a function of the time of their registration, and for identical addresses of blocks 2 and 3 there is a one-to-one correspondence. In the seismic information source (track), this correspondence may not appear in its new form due to the imposition of interference waves on useful waves, which usually have a different spectral composition. An external trigger pulse in the form of voltage is fed to the reset inputs and the zero address counter of the control unit 1 (Figures 1 and 2) and the first input of the OR 6 element, from the output of which enters the counting input of the counter 1, is set to its address output code equal to one. This pulse at the output of the delay element T1 forms the control information read signal simultaneously from block 2 of the memory of seismic signals and block 3 of the memory of the fundamental frequency table at the address determined by the contents of counter 10, the output of which is connected to the address inputs of memory blocks, In this case, the first readout of memory block 3 is fed to the input register of the converter 9, the code-time interval, i During the pause, the converter 9 is equal to the product of the code selected from block 3 for the period of the clock pulse the generator of the converter 9, the signal of the second delay element 12 after the end of the reading cycle from block 2 ((setting addresses and sampling the signal to the information buses, the code sample of the seismic signal goes to the DAC register, this starts the digital-to-analog conversion with the same signal from delay element 12, the analog-to-digital conversion cycle in the ADC 7 of the analog signal from the output of the filter 5 begins. Moreover, the response of the filter at the output always lags behind the input disturbance. Signal The end of the code conversion, the sample of the filtered signal is copied from the output of the ADC 7 to the register 8. The control signal is recorded from the output of the third delay element 13 of the control unit 1, the code from the register 8 is written to the memory unit 2 at the address specified by the content counter 10. At the time of the end of the pause, the minimum time of which must exceed the conversion time and the cycle to access block 2, the output of the converter 9 generates a read-write signal that goes to the swarm input of the IL element 6 and further to the counter 10, increasing the state of the last unit, and the process is repeated. Further, the asynchronous voltage pulse stream, determined by the code sequence of the fundamental frequency table, from the output of converter 9 controls the speed of movement of the code sequence of seismic signals around the ring: memory block 2 - D / A converter k - filter 5 - ADC 7 register 8 - memory block 3 ti with the transformation of the main frequencies of seismic signals at the output 111AP

kri)

(t

(2)

At

e f,

transformed basic

fci signal frequency at the output of the DAC, for the 1st sample;

A - sampling interval of the original seismic signal;

ci is the fundamental frequency of the seismic signal for i- and sampling;

 - the value of the i-th sample of the base frequency table;

С is the period of the following t5 pulses.

From expression (2) it is clear that if the seismic signal’s basic frequency exactly corresponds to its tabular value, for each sample (or rather, in the vicinity of the sample), the transformed basal frequencies of the seismic signals at the output remain constant and thus vary in filtering time at a constant filter

The proposed device is used to isolate the useful component of seismic waveforms.

with continuous change of their basic frequencies.

Since the operation of the memory blocks, DAC, ADC, taking into account the parallel operation of the converters, does not exceed several microseconds in order to achieve the greatest possible device performance, the minimum pause size can be taken equal to 10 microseconds. Assume that changes in the fundamental frequencies of seismic signals lie within the range of 6010 HZ. If the period of the following pulses of the clock generator of the converter 9 is equal to 1 μs, then the minimum pause worked out by the converter 9 will obviously be equal to 10 μs. From expression (2), the fundamental filter pass rate, taking into account the usual coding practice with / at, will be equal to 2000 Hz. The transformed bandwidth can also be determined from the expression (2 J, but is controlled directly in the filter itself.

The economic efficiency of using the proposed device is determined by the reduction in cost due to the exclusion of the computing unit and the increase in productivity by an order of magnitude.

Claims (2)

1. DEVICE FOR PRIMARY PROCESSING OF SEISMIC INFORMATION, containing a control unit, the first and second outputs of which are connected respectively to the first and second inputs of the first and second memory blocks, a digital-to-analog converter, the information input of which is connected to the output of the first memory block, the control input - to the third output of the control unit, and the output to the input of the bandpass filter, characterized in that, in order to simplify and improve performance, an OR element, an analog-to-digital converter, a register are introduced into it a code-time converter whose input is connected to the output of the second memory unit, and the output through the OR element is connected to the input of the control unit, the fourth output of which is connected to the third input of the first memory unit, the information input of the analog-to-digital converter g is connected to the output of the strip filter, the control input is with the third output of the control unit, and the output through the register is with the fourth input of the first memory unit. > 2. The device according to π.1, wherein the control unit contains an address counter, the output of which is the first output of the unit, and the input is the input of the unit and connected to the input of the first delay element, the output of which is the second output of the unit and input the second delay element, which is connected to the input of the third delay element and with the third output of the block, the output of the third delay element is connected to the fourth output ^{1 of the} block.