SU1056251A1 - Device for compressing information - Google Patents

Abstract

A DEVICE FOR COMPRESSION OF INFORMATION containing an information block, the first input of which is connected to the input information bus and to the primary input of the clock extracting unit, the first B4 stroke of which is connected to the first input of the block of key elements, the first input of the memory block of the argument and the second input of the memory block information, the third input of which is connected to the second output of the clock selection pulse and to the second input of the argument argument block, the first output of which is connected to the first input of the aperture memory block argument Nta, the second input is connected to the aperture control bus of the argument, the output is connected to the first input of the comparison unit, the argument, the second one. the input of which is connected to the second output of the argument memory block, the third input of which is connected to the second input of the key element block, the output of which is connected to the output information bus, the third input of the key element block is connected jK to the first output of the information storage block, the second output of which is connected to the first the input of the comparison block: no function, the second input of the comparison block of the function is connected to the control bus of the function aperture, the first output is connected to the input of the sign selector, the second output is connected to the fourth input of the information storage block and, to the fourth input of the block of memory of the argument and to the first input of the first element And, the output of the first element And connected to the fourth input of the block of key elements, the second input - from above. the argument block comparison process, characterized in that, in order to increase reliability by fixing the time of occurrence of a significant count, a device (L entered the second AND element and a trigger, the single trigger output connected to the first input of the second AND element, the second input of which is connected to the first output of the sign selector, the second output of which is connected to the fifth input of the key element block, the output of the second element I is connected to the third input of the argument memory block and the second input of the key element block, the sixth input which is connected to the third output of the argument's block, the fifth input of which is connected to the output of the first AND element, the fourth output to the second input of the block of clock pulses, the first output of the block; Clock pulses are connected to the input of the zero setting a trigger whose unit setup input is connected to the second output of the function comparison unit.

Description

The invention relates to a measurement information technology iH can be used in various information transmission and processing systems. A device for compressing information that contains a memory block, a function comparison unit, a character definition unit, an argument comparison unit and a block of key elements I are known. The disadvantage of this device is that it does not provide high accuracy of restoration because it does not allow to fix and form local extremums for transmission to the receiving side. The closest in technical essence to the inventions is a device for compressing information containing a memory block, the first input of which is connected to the input bus, the first output and the second input of the m block, respectively, are connected to the first input and the first output of the first comparison block, the second input of which is connected to the control bus of the aperture of the function, the second output of the first comparison unit is connected to the input of the sign determining unit, the output of which is connected to the first input of the block of key elements whose output is connected to the output bus, the second comparison block., the argument aperture block, the inputs of which are connected to the argument aperture control bus and to the first output of the argument memory, whose inputs are connected to the outputs of the clock pulses, and the third and fourth inputs of the memory block and with the output of the sign determining unit, with the first: element I, with the first output of the first comparison unit and with the first output of the second comparison unit, the second output of which and the second output of the argument memory block are connected to the first input of the memory block and to the second input And, the output of which, the second output of the memory block, the third output of the second memory block, the sixth input of the memory block and one of the outputs of the block. The clock pulse selection is connected to the second, third, fourth and fifth inputs of the block of key elements, the input of the block clock extraction is connected to the input bus, the fourth input of the argument memory block is connected to the second input of the second comparison block, the third input of which is connected to the output of the argument aperture block. The device makes it possible to precisely fix the points of essential samples necessary for linear interpolation, and, in particular, to select points with an amplitude of local extremes 2. However, the known device does not allow to determine the exact time of occurrence of a local extremum, since the number of clock pulses between the instant of local extremum and the instant that it is determined that this point is really local extremum is not constant. It widely depends on the rate of change of the recorded process and on the size of the aperture. As a result, the accuracy of the measurement of the measured signals is reduced. By accepting significant readings at the receiving side. In addition, it is not possible to estimate the parameter at the current time (unless, of course, there is a significant reading at the current time). According to the substantial readings received at the receiving side, the recovery is carried out back: it is considered that significant readings of the meid can be approximated by a linear function, i.e. the change of the measured function from the last significant reference to the current time interval is not restored. This can significantly reduce the efficiency of controlling the flow of the process being measured. The aim of the invention is to increase the reliability of information by fixing the time of occurrence of a significant count (and, in particular, local extremum) and to ensure the possibility of estimating a parameter from the last significant count to the current moment-time. The goal is reached flowed into the compression device. information block containing an information memory block, the first input of which is connected to the input information bus and to the first input of the clock selection block, the first output of which is connected to the first input of the key element block to the first input of the argument memory block and to the second input of the information memory block the third input of which is connected to the second output of the pulse extraction unit and to the second input of the argument argument block, the first output of which is connected to the first input of the memory block of the argument aperture, the second input is connected to the aperture control bus of the argument, and the output is connected to the first input of the argument comparison block, the second input of which is connected to the second output of the argument memory block, the third input of which is connected to the second input of the key element block, the output of which is connected to the output information bus, the third the input of the key element block is connected to the first output of the information storage block; the second output of which is connected to the first input of the function block; the second input of the function comparison block is connected to the control bus functions, the first output is to the input of the sign selector, the second output is to the fourth input of the information storage unit, to the fourth input of the argument storage unit and to the first input of the first element whose output is connected to the fourth input of the block of key elements, and the second input is the output of the argument comparison block, the second element I and the trigger are entered, while the single output of the trigger is connected to the first input of the second element AND, the second input of which is connected to the first output of the sign selector, the second output of which is connected to the fifth input of the block the key element, the output of the second element I is connected to the third input of the argument memory block and the second input of the key element block, the sixth input of which is connected to the third output of the argument memory block, the fifth input is connected; to the OUTPUT of the first element AND, the fourth the output is connected to the second input of the clock extraction unit f, the first output of the clock selection unit is connected to the input of the zero setting trigger, the input of which is e; the pixels of which are connected to the second output of the function comparison unit. And the drawing presents the structures on the scheme of the proposed device. The device for compressing information comprises an input information bus 1, a clock input unit 2, an information memory block 3, an array of three ger 5 argument block 4, a key element block b, an output information bus 7, a character selector 8, a function comparison block 9, the aperture control bus 10 functions, the elements 11 and 12, the argument aperture memory block 13, the argument aperture control bus 14 and the argument comparison block-15 / The blocks included in the device can be executed in a different way. The following are schematic reagent options. blocks that have been tagged and tested at the enterprise. The clock extraction unit 2 includes a time delay element as well as an element for selecting the first pulse and subtracting the first pulse from the pulse sequence. The information memory block 3 includes the OR element and two registers 1 triggers: an input register and a memory register. Argument memory block 4 includes a DEOichny counter, register) triggers, two decoders and a delay element. BLOCK b of the key elements includes the OR element, the register D-tr; iggers, bit keys and the output driver; the sign selector 8 contains the comparison elements, the D-trigger and the delay element. Block 9 of the comparison function contains two input registers, the aperture register, the adder, the comparison elements and the delay elements. Argument aperture memory block 13 contains two registers of D triggers S apertures and argument apertures, a division scheme. Argument comparison unit 15 contains two input registers for D triggers, an adder, comparison elements and delay elements. The remaining blocks, which are part of the proposed device for compressing information, are standard and do not require special clarification. The inputs to the device for compressing information are sensor signals in the form of voltage (analog form) or code messages (digital form), which are accompanied by clock pulses of a strictly fixed frequency. For the sake of simplicity, suppose that the compression device only serves one-one. the sensor (single-channel processing system), which gives the code parcels, and the frequency of the X pulses accompanying each code parcel, is such that even with the most rapid change of the input signal, the difference in two consecutively incoming codes in the device does not exceed the unit of the least significant bit. In this case, the proposed device for compressing information works as follows. Code packages with a constant, known number of bits, reflecting the sensor signals, are fed to the input of the device for compressing information with a serial (or parallel) code accompanied by clock pulses along the input information bus 1. Clock pulses accompanying code packages are analyzed in block 2, the allocation of clock pulses, in which ocyt; i.e., is the delay of clock pulses by the time required for conversions, and is also divided into two outputs. The first pulse arrives at the output of the first pulse, which arrives after the device is turned on, and also the first pulse after the arrival of an external input signal. All the rest takovye pulses, accompanied by the sending code packets, are inserted at the other output - the output of the current pulses. Each code message is stored in the input register of the information storage block 3 However, if the input signals have a certain form, for example, parallel code messages, constant between the clock pulses accompanying them, the input register need not be used, and the input code message is used as its output signals ). Let us first consider the operation of the proposed device at the time of posting the first code parcel after switching on the measurement system. The first code dressing is always essential. After the code of the first parcel has been formed on the input register of the information storage block 3, the clock extraction pulser 2 generates a pulse at the output of the first pulse. This pulse enters memory block 3, where it installs. in the register of memory contents equal to the contents of the input register of the same block. The pulse — from the output of the first pulse of the clock extracting block 2, also goes to the argument memory block 4, where it sets the counter and the register to zero, and to the trigger 5, sets the zero inhibit signal at its single output. The same impulse is delivered to the block b of key elements, where it opens the keys for progression to the output information bus 7 of the essential counting code. From the output of the parallel code of block 3 (the invention does not depend on which of the two registers of block 3 is connected to the output parallel code if the input register is connected, then the transfer is carried out in natural time scale, and the exact value of the extremum is calculated, if the memory register is connected to the contrary, then the exact value of the local extremum is subject to transmission, and the moment of its occurrence and the value of the current sensor reading are calculated 5, let the latter be chosen for definiteness). In addition to the significant sample code, the same output bus 7 will receive a code from the output of the current time of block 4 of the argument memory / fa in this case - after setting this block to zero - a zero code), as well as the code from the sign definition block 8 ( in this case, the form of this code is indifferent, since the code introduced by the memory 4 block of the argument zero does not change with any sign of this code). The following code messages arrive on the input information bus 1 to the block, 3 information memories and to the block 2 for the selection of clock pulses. In this case, the parallel code of the input code parcel is legalized on the input register of the information storage block 3. Thereafter, at the output of the current pulses of the clock extraction unit 2, a delayed clock pulse is generated, which enters block 3 and block 4. The pulse arriving at block 4 increases the content of the counter of this block by one, and the pulse received in block 3, at its output of two codes, the codes of the input register and the memory register are formed. These two codes post on block 9 of the function comparison. Block 9 determines the modulus of the difference of both input codes and compares this value with the permissible aperture value set by the function aperture control bus 10 signals. If the difference module does not exceed the allowable one, block 9 does not issue control parcels, but already when the module is one less than the least significant bit of a difference, the block 9 issues code packets arriving at block 9 from block 3. These codes are sent to selector 8 characters which determines which of the two codes is greater. If the code on the input register of block 3 exceeds the code on the memory register of block 3, then a logical zero is formed at the information output of block 8, and if the code on the memory register is larger, then the logical unit. This result is compared with the code in the memory element of the selector 8 and, after a delay, is entered into this memory element. If the comparison result does not coincide with the previous comparison, recorded in the storage element (i.e., a local extremum was selected during the comparison), -Tb. After a time fixed at the control output of the sign definition selector 8, a pulse is generated that is received at the first input Element 11, Trigger 5 is in the S zero state when first comparing the characters after the pulse has been selected at the output of the first one, the pulse of the clock selection block 2 and in the single state for any other comparison of characters. Thus, for any comparison of characters other than the first, the impulse from the Comparison Output 8 of the selector 8, if it is vigilant, passes element 11 and enters block 4 of the argument memory and block b of key elements.

In block 4 of the argument’s memory, the pulse is transferred to the register in this register,

In block b, the pulse opens keys 0 for passing to the output information bus 7 of the code of substantial counting from the parallel output (soda of block 3; In addition, to the same bus

7, a code is received from the informational 15 output of the sign determining selector 8 and the code from the output of the current time of the argument memory block 4. At the output of the current time of block 4, the counter codes are connected, and a local extremum code is generated at the output of the parallel code of block 3. To determine which time interval separates the occurrence of a local extremum from the current moment, 25 it is enough to multiply the code at the output of the current time of block 4 by the period of clock pulses (this can obviously be done after the receiving side), If at the information output of the selector 8 characters If a logical zero is present, then to determine the signal at the current time, it is sufficient to add to the code at the output of the parallel code of memory block 3 an aperture value 35 and a signal value equal to one least time code information.

In this case, if a logical unit is present at the information output of the B selector of the sign, it is sufficient to subtract 40 for determining the signal at the current time.

from the code at the output of the parallel code of block 4 of memory, the aperture value and signal size equal to 45 units of the lower order information code. Since all the necessary codes are transmitted to the receiving side, the calculations are not difficult to perform on. reception cn side.

After the required time for conversions, the period of time after the block 9 gives out the code parcels, the control output of this block appears 55

pulse. It transfers the trigger 5 to a single state, enters the first input of the element 12, enters block 3, where after the necessary delay it rewrites it into. 60

the memory register is the contents of the input register and is supplied to the block 4 of the memory of the argument.

If the register of block 4 is zero.

code (which can only be for 65

When block 9 is the first time pulse per block 4 after generating a pulse signal at the output of the first ushusha of the clock selection block 2), the contents of the counter of block 4 are transferred to the register of block 4. The code from the register of block 4 is transferred to block 13 of the aperture memory of the argument . In addition, in block 13, the code relative to the aperture of the argument is supplied via the aperture control bus 14 of the argument.

From these two values, the argument aperture memory block 13 calculates the absolute value of the maximum permissible deviation of the argument. For example, a 20% tolerance is set on the argument aperture control bus 14. If code 20 is set on the register of block 4, then code 4 is formed at the output of block 13, if code 100 is set at the register of block 4, code 20 is output at block 13, and so on. The output potentials of the counter and the register of the argument memory block 4 are connected to the argument comparison block 15, which finds the modulus of their difference and compares with the code from the memory block 13 of the argument aperture. If the modulus of the difference between the codes of the counter and the register of the argument's 4 memory block exceeds the permissible value of the largest deviation of the argument, then the block 15 of comparing the argument generates a signal of a logical unit. With the coincidence in time of this signal and the pulse at the output of the control unit 9 compare. In this case, a pulse signal is formed at the output of the And 12 element. This signal overwrites the contents of the counter of the same block into the register of block 4 of the argument memory. In addition, the output pulse of the element 12 is supplied to the block b of key elements, where it opens the keys for passing to the output information bus 7 the essential code from the output of the parallel code of block 3 of the code from the information output of the selector 8 character and the code from the current time of memory block 4 ti argument.

In addition to the indicated impulse from the control unit 9, the function comparison unit 9 additionally performs the initial setting of the counter in block 4 of the argument memory: after j, a delay of sufficient time to issue the required codes to the output bus 7 (if necessary), the pulse resets to zero: the contents of the counter in block 4 of the argument's memory.

However, in principle, this counter, like any other, can be reset to zero by other means:

when the next pulse arrives, if units in all bits are set in the counter. With such a setup, which is not ruled out with the last & changes in the input signal, a methodical error in time appears. To avoid it, into a block. The 4 argument memories are entered to the decoder which responds to the single state in all paapjwax counters. The next clock pulse should not get into the counter. Therefore, the output of the decoder is connected to the control input of the clock extracting unit 2, i.e. After all the units are in the counter, the next clock pulse of unit 2 is generated at the output of the first clock pulse. In this case, as discussed, the materiality of the current reference is compulsory, as well as the initial installation of blocks 3 and 4 and trigger 5.

The use of the invention increases the reliability of the device and the accuracy of information recovery by 20-30%.

Claims (1)

A DEVICE FOR COMPRESSING INFORMATION, containing an information memory block, the first input of which is connected to the input information bus and to the first input of the clock selection block, the first output of which is connected to the first input of the key element block, the first input of the argument memory block and the second input of the information memory block , the third input of which is connected to the second output of the clock allocation block and to the second input of the argument memory block, the first output of which is connected to the first input of the argument aperture memory block the one whose second input is connected to the argument aperture control bus, the output - with the first input of the comparison unit, argument, second. the input of which is connected to the second output of the argument memory block, the third input of which is connected to the second input of the key element block, the output of which is connected to the output information bus, the third input of the key element block is connected ίκ to the first output of the information memory block, the second output of which is connected to the first input function comparison unit, the second input of the function comparison unit is connected to the function aperture control bus, the first output is to the input of the sign selector, the second output is to the fourth input of the information memory block, to to the first input of the argument memory block and to the first input of the first AND element, the output of the first AND element is connected to the fourth input of the key element block, the second input is with the output of the argument comparison block, characterized in that, in order to increase reliability by fixing the appearance time of a significant reading, the second element And and the trigger are introduced into the device, the single output of the trigger is connected to the first input of the second element And, the second input of which is connected to the first output of the sign selector, the second output of which is connected to the fifth the key element block, the output of the second AND element is connected to the third input of the argument memory block and the second input of the key element block, the sixth input of which is connected to the third output of the argument memory block, the fifth input of which is connected to the output of the first AND element, and the fourth output to the second the input of the clock imparting unit, the first output of the clock allocation unit is connected to the trigger zero input, the unit setting input ^ of which is connected to the second output of the function comparison unit.