SU1043747A1 - Storage with multi-format access to data - Google Patents

Abstract

MEMORIZED. SETUP WITH INTERPRETING DATA ACCESS TO DATA, containing type register, accesses, register, modulo dukd sukmat, data multiplexer unit, data register and memory unit, with the output of type typing registers, connected to the output from the inputs, two equalizer, the output of which is connected. it with the first address input of the memory block, output of the soy address register. It is connected to the control input of the data multiplexer unit, the output is costly connected to the data register input, so that, in order to expand the scope of application by providing. the ability to access square data fragments, an I element, an address code multiplexer block and a second data multiplexer block are entered, the input of the AND element is connected to the register type output, and its output is connected to the control input of the multiplexer code of the address code and control input the second block of multiplexers is given Hbjx, the input of the block of multiplexers of the address code is connected to the output of the address register, and its output is connected to the second address input of the memory memory and the second input of the C-modulator two, the input of the second Lok data multiplexers connected to the data output unit TZM C ti, and its output - to the input of the first block of data multiplexers. 4 CO 4 41

Description

The invention relates to computing, namely to the section of storage devices that can be used in specialized storage systems and digital image processing, as well as in associative computing systems. A storage device is known in. O for storing digital two-dimensional arrays of data (images) :, allow to make access to columns, rows, and rectangular image fragments fl, This device uses pq + l memory integrated circuits with a pq capacity of bits each One access to one bit, 6, does not extract a row or column containing pq elements or a fragment with a maximum size of the sides p and q. The image point with the coordinates L and Г, where L and I are integers from zero to pq, falls into an integrated memory chip, the number of which N is calculated using the formula M ft + T1, / N (Lq, Pspos1 (rf, 4 -d) Such a system is universal, however, a large amount of equipment is necessary for its implementation. The closest to the proposed technical essence is an associative memory, a device containing the address register, the address register, the modulo adder, the data multiplexer block , .register data and memory, and the output register type The access is connected to one of the inputs of the adder by modules two, the output of which is connected to the first address input of the memory block, the output of the register of the address is connected to the control input of the data multiplexer block whose output is connected to the input of the data register. The device is built on integrated memory chips with a capacity of 2 bits each, where and, 2, 3, ... For storage of information, W integrated memory chips are used, i.e. as much as the elements of the matrix of the binary image must be selected simultaneously. The memory block can be built on integrated chips with a larger capacity of 2 W, while the image matrix will be composed of square submatrices with a side of W. To implement multi-format (to sides and columns) access, elements of the memorized matrix (WW binary array) are placed in Ps1m integrated circuits in such a way that all elements of any row or column fall into different memory chips. This ensures the possibility of simultaneous sampling of an arbitrary row or column. . To describe the correspondence between the elements of the memorized matrix and the numbers of the integrated memory chips and the addresses, the following symbols are entered in them: I, t is the number of the column and the rows of the memorized matrix I 04 W -1 -1,0 4 W -1; N is the number of the Integral microsseed, memory .N OFN W - 1 J A-R - the bit size: address code, which determines whether a bit is embedded in one memory chip; -S- is the type of address code. Specific values of L, I, N, A, S can be considered as binary vectors and denote the corresponding L, - I, N, A, S. In the following, the special operations of conjunction (L), disjunction (V), addition modulo are used. two) and negations (-) over binary vectors. For example, С х.Л у means that С- (,,.., С0) (, х., .2ЛУЛЛ- -. And Wo). 0, each binary element of the memorized matrix with coordinates L, I is stored in the microcircuit, the number of which is determined from the relation. N For supplying addresses to memory chips, two buses are used, x and y. Bus X is fed with the address code from the device's address register. On the bus, the code comes from the output of the sum- :. modulo two, whose input is x and, moreover, y (5. The S code comes from the call type register. The connection rule for the address entries in the memory block of the following code: address inputs A (ajj. and jj.2 o) Those with the number N (n,.,) are connected to the bus wires (Uk - 1 Un.-2 "OA corresponding bits of the number of this chip is one, and the natural inputs are connected with the corresponding wires of the bus X. The circuit of this connection is described A - (N) V () expression (1), which determines the distribution of its row elements (columns) by m memory chips, indicates that for different rows (columns) the order of the elements on the wider memory blocks will be different. This order for the columns (column) with the number L (I), as seen from expression (1), is defined The corresponding diode (modulo two) shifts. To ensure unambiguous ordering when sampling any row (column) in a device, a data multiplexer unit consisting of english is used. Each rus implements a permutation of the elements of the row (column); corresponding to the diode shift. certain (2, 2, 2, ..., ...,) order. Control the inclusion of ru-. The combination of the data multiplexer block depends on the state of the corresponding bits & address code1. .

From expression (2) it follows that, if the vector S is completely zero, on the address inputs of all the memory chips, regardless of the number, there is T {od, equal to the code on the bus x. The same address on all microcircuits / corresponds in the device to the row selection mode.

If S is a completely single vector, then the expression. (2) is converted to a form. .

© N

A X

From the expression (3) it follows that for a given X in all .N chips. Memory bits are selected at different addresses. This corresponds to the mode of reference to the columns of the stored matrix. and

With .0 S 2 - 1, mixed handling methods are obtained, in which a sample of different combinations of parts of rows and columns of the matrix is realized. ..

The memory, constructed according to the principles described, is characterized by simplicity and large functional possibilities. but ti mi.

However, this memory does not allow the sampling of a square vw () fragment of a matrix on a single inversion. Covering them with a six-digit field of the binary image. At the same time, the need for such data sampling is often found in digital image processing systems and in associative arguments. . . . . The aim of the invention is to expand the range of application of the associated memory device to digital image processing systems and to increase the efficiency of its use by introducing additional memory access formats to reduce the number of references when working with square fragments, images.

The goal is achieved by the fact that in the scheme of a memory device containing a register, such as.-J forms, the register of the address, the sum is. ji tor modulo two, block multiplex - :.

data logs, a data register and a memory block, the output of the type of reference register is connected to one of the inputs of the modulo two adder, the output of which is connected to the first address input of the memory block, the output of the address register is connected to the control input of the data multiplexer block, the output is directly connected to the input of the data register, the AND element is entered,

0 is a block of code-address multiplexers and a second block of multiplexers. data, and the input element And is connected to the output of the register type of appeals, and. its output is with the control input of the multiplexer unit of the address code and the control input of the second block of data multiplexers, the input of the multiplexer unit of the address code is connected to the output of the address register, and its output is connected to the second address input of the memory unit and the second input modulo two,

.input of the second data multiplexer unit. connected to the information

the output of the memory block and its output to the input of the first data multiplexer block. .

FIG. 1 shows a schematic diagram of the proposed device on

-fig 2 - the correspondence between the elements

0

the memorized matrix and the addresses of the integrated memory chips in which they are stored. W, 16, in fig. 3 is a block diagram of FIG. 4 -g permutations made by the second data multiplexer unit (“) and the first unit of the data multiplexer units (G, C, D, E).

The block diagram of the storage device contains the element And 1

on R inputs ,, register 2 types of references, adder 3 modulo two, memory block 4, second-block 5 data multiplexers, first block 6. data multiplexers, data register 7, address register 8, block 9 multiplexers of the address code. Taka. The structural scheme was developed by the following changes in the distribution of the elements of the matrix and the memory integrated circuits. The new distribution is described by the expression

N (/ Lw / ,,.

(four

where N is the number of the microcircuit n am, in which the element of the aforementioned matrix with the coordinates L and I falls into; square string fragment; .., taking the whole part of x.

X As can be seen from the table shown in FIG. 2, at this time. It is possible to apply them to square fragments with a side W. In FIG. 2, it is highlighted in bold 5 lines. In order to implement this distributed, it is necessary for all calls, except for addressing by columns, the address coming from the address register to shift by R / 2 bits cyclically or, which is the same, rearrange the high and low bits on the address buses. New order doc. Xf wires, the following:

 PgCh 12-2

 0VlR-2

In addition, when accessing the columns, the second data multiplexer unit should be included. The inputs of this unit are connected to integrated circuits, memory. When the second multiplexer unit is on, the output of the memory chip with the number is switched to the N line, the number of which is calculated by the formula

N -w / N /. N / W. .

Thus, when addressing by columns, the second data multiplexer unit is turned on and the multiplexer block of the address code is turned off, and for the remaining calls, the second data multiplexer block is turned off, and the multiplexer block of the address code is turned on. The control inputs of the first data multiplexer block always receive the code x ".

Consider a few examples for W 16.

Example 1. Suppose X-0110 ,. When a call occurs in rows, and with a given X, the call should occur on the sixth line. Since the conversion does not occur in columns, the block of multiplexers, code ad-, is included. rez and X is shifted two times cyclically

XH 1001;

Y S0X 00000

) 01 1001.

From the diagram presented on FIG. 3, it can be seen that with the random values of X and Y on all the memory chips, the address is 1001. This corresponds to the sixth distribution line, the order of the data in which is the following:

9,8,11,10,13,12., 16,14,1,0, 3,2, 5,4,7,6.

This means that the information from the ninth memory chip should go to the first data wire on the first wire - information from the eighth memory chip, etc. For this conversion, data multiplexer blocks are used. The second data multiplexer unit is not included in this case, and the first

controlled by the .tUOl code. In the first block of multiplexers, the DPs include the zero and the third Russ permutations (in FIG. 4.5) and. information at the output of the block is in the normal form: 0.1,

2.15.

Example 2. Let,. Reversal occurs in columns, and the block of multiplexers of the address code is not included.

U 11101000 0111

When., The memory chips will have the following addresses: on the chip O - 1000, on the chip 1 - 1001, on the chip 15 0111.

As can be seen from the table of information distribution (Fig. 2) at the given addresses, the reference corresponds to the eighth column, where the order of information is the following

8,12,0,4,9,13,1,5,10,14,2,6,11, .15,3,7. ,

After conversion, the first block of data multiplexers will be as follows:

2,3,0,1,6,7,4,5,10,11,8,9,14,15,

12.13.

This means that the information from the second wire of the Yes bus should reach the neutral wire, with

the third wire - on the first, etc. This conversion performs the second data multiplexer unit, which is controlled by code 0010 (i.e., shifted X).

Example 3. Let,. There must be an appeal. to fragment number one.

Hz 0100, U 110000100 1000. At the address inputs of the microcircuit there will be the following address codes: on the chip O - 0100, on the microcircuit 1, - 0100; on the microcircuit 2 - 0100, on the microcircuit 3 - 0100, on the microcircuit 4 - 0000, on the microcircuit 14 1000, on the microcircuit 15 - 1000.

The information on the above data corresponds to the first fragment. The order of information is as follows:

4,5,6,7,0,1,2,3,12,13,14,15,8,9; .10.11.

The first block of data multiplexers is turned on, which is controlled by code 0100 and transforms the information to the desired form.

Introduction to the memory circuit of the multiplexer block of the code of the grid address, the second block of data multiplexers and the And element slightly complicates the circuit of the proposed device, but gives

l.iye advantages compared with the known. Application of the proposed storage device for digital image processing systems

.-- i-l; 3-:;

significantly increases its efficiency by reducing the number of memory accesses by w times when working with square fragments.

Claims (1)

. MEMORY DEVICE WITH MULTI-FORMAT DATA ACCESS, containing type register, access, address register, modulo adder V two, a block of data multiplexers, register and a memory block, and the output of the register of type the input of the block of data multiplexers, the output of which is connected to the input of the data register, which differs from · in that, in order to expand the scope of application due to the provision. the possibility of accessing square pieces of data, the element And, the block of address code multiplexers and the second block of data multiplexers are introduced into it, the input of the element And is connected to the output of the call type register, and its output is connected to the control input of the block of address code multiplexers and the control input. block of data multiplexers, the input of the block of multiplexers of the address code is connected to the output of the address register, and its output is connected to the second address input of the memory block and the second input of the adder modulo two, the input of the second mule block tipleksorov data connected to the data output of the storage unit, and ogo output - to the input of the first block of data multiplexers. SU 1013747 1Ό43747 "th?