SU1042153A1 - Device for pulse-phase control of thyristor converter - Google Patents

Abstract

DEVICES FOR IMPULSE PHASE CONTROL OF A TYPE DISTRIBUTOR TRANSMITTER, containing a controllable generator, the first binary counter, the output of which is connected to the first input of the match block, the AND element, the synchronization unit with the synchronizing output and the distributor, has been added and, in order to increase, the synchronization unit with the synchronizing output and the distributor, with the purpose of improving with the purpose of raising the synchronization unit with the synchronizing output and the distributor, with the purpose of increasing the synchronization output with the synchronizing output and the distributor, with a purpose phase angle of control at a variable frequency of the power supply network, it is equipped with a stable frequency generator, second and third binary counters, a memory register, a time delay element, an I- element NOT, ftC-trigger, and the synchronization unit - additional high-frequency output, the output of the controlled generator is connected to the counting input of the first binary counter, the synchronized output of the synchronization unit is connected to the inputs of the first and third binary counters and the R-input RS-trigger, high-frequency the output of the synchronization unit is connected to the counting input of the third binary counter, to the overwriting input of the memory register and, through a time delay element, to the reset input of the second binary counter, the counting input of which is Connected to the output of a stable frequency generator, the output of the second binary counter is via a re (L memory girder is connected to the second input of the match block, the output of which is connected to the first; input; And element, the second input of which is connected to the output of the NAND element, whose inputs are connected to the corresponding (Third-party binary output counter G6, the output of the AND element is connected to the S-input of the P5 flip-flop, 4 inverse and the direct outputs connected, respectively, to the input of the prohibition of the account of the first counter and to the input of the pulse distributor control.

Description

The invention relates to electrical engineering and can be used in devices for controlling the phase of control pulses of thyristor converters. A device is known for pulse-phase control of a phase thyristor converter containing a controlled pulse generator, a pulse counter, synchronization elements, logic elements 1.- Known also a device that implements the method of controlling the angle, unlocking the valves, containing the synchronization unit, the counters, the generator being controlled, the half-wave selection unit of the power supply apr wife The disadvantages of these devices are the change in the phase angle of the output pulses when the voltage is varied within wide limits of the frequency of the supply network, and the absence of limitations of the phase angle on the maximum allowable value. The closest to the proposed software technical entity is. A device for pulse-phase control of a thyristor converter, containing a controlled oscillator, a first binary counter, the output of which is connected to the first input of the coincidence unit, an AND element, a synchronization unit with a synchronizing output and a C 3 distributor. The disadvantages of this device are the change in magnitude phase angle of the output pulses with a change in the wide frequency of the mains supply frequency and the absence of limiting the phase angle to the maximum allowable value, which reduces the reliability of spinner The aim of the invention is to increase the stability of phase angle control at a variable frequency of the power supply network. The goal is achieved by providing a device for pulsed phase control of a thyristor converter equipped with a stable frequency generator, second and third binary counters, memory register, time delay element, element NAND, RS-flip-flop E) OM, and the synchronization unit an additional high-frequency output, where the output of the controlled generator is connected to the counting input of the first binary counter. ka, synchronizing the output of the synchronization unit is connected to the reset inputs of the first and third binary counters and the R input of the RS is three meters, the high frequency output of the synchronization unit is connected to the counting input of the third binary counter, the memory register overwriting input and through the time delay element the second reset input generator of stable frequency, the output of the second binary counter through, the register is connected to the second input of the matching block, the output of which is connected to the first input of the element And, the second input of which is connected to the output of The NAND input whose input is connected to the corresponding bit outputs of the third binary counter, the output of the AND element is connected to the 5th input of the H5 flip-flop, the inverse and the direct outputs of which are connected respectively to the input of the prohibition of the counting of the counter and to the input of the control pulse distributor. The drawing shows the functional diagram of the proposed device ... The device comprises a coincidence unit 1, one multi-bit input of which is connected to a multi-bit. the outputs of the first counter 2. The counting | input of the first counter 2 is connected to the output of the controlled generator 3, the input of which is connected to the output of the source 4 of the control voltage. The synchronization output of the synchronization unit -5 is connected to the reset inputs of the first and third counters 2, b and the R input of the RS flip-flop 7. The high-frequency output of the synchronization unit 5 is connected to the overwriting input of the memory register 8, to the counting input of the third counter, b and through the element 9 of the time delay to the reset input of the second counter 10, the counting input of which is connected to the output of the stable frequency generator 11. The multi-bit counter output 10. is connected to the multi-bit inputs of the memory register 8. The multi-bit 5 OUTPUT register 8 is connected to the other multi-bit inputs of the coincidence unit 1. The output of the coincidence unit 1 is connected to the first input of the element 12, the second input of which is connected to the output of the element. I-NE 13, the inputs of which are connected to multi-digit outputs e 1 of the sensor b, the output of the element I 12 is connected to the 5-input of the RS flip-flop 7. The inverse and direct outputs of the RS-xpHrrepa 7 are connected respectively to the inhibit input of the counter 2 and the distributor 14 control pulses on thyristors. The device works as follows. The synchronization unit 5 produces, at a synchronizing output, pulses with a double frequency of a 2-second power supply network, the phase of which corresponds to the natural switching points of the thyristors of the converter, and at the high-frequency output — pulses with a high frequency of 2 kf s, a multiple of the frequency of the pulses of the synchronizing output (I is integer number). The pulse of the sync output as a logic zero signal is fed to the reset inputs of counters 2 and b and the R input of R5-trigger 7.. Counters 2, b are zeroed, the signal of the logical unit is set at the inverse output of RS-trigger, which allows the counter 2 to count The generators of the stable frequency generator 11 in I are considered to be counted for a time Yu and are copied to the register 8 of the high-frequency output of the synchronization unit 5 as a binary code. The impulse of the high-frequency output of block 5, delayed by the element of volume 9 of the time delay, resets the counter 10. At one output of block 1 of coincidence, the output from register 8 is received as a binary code of a number proportional to period 1. of the mains and equal at the other input of block 1 coming from the output of counter 2, varies in time with the speed / detectable frequency of the generator 3J which, in turn, depends on the value of the control voltage supplied to the input of generator 3 from the output of block 4. At the moment the codes are equal to The inputs of the coincidence unit 1 at its output appear a logical zero signal, which through the logic element And 12 is fed to the S input of the RS flip-flop 7 and sets the logical one signal at the forward output of the RE-flip-flop 7, and the inverse logical zero signal . In this case, through the distributor 14, the signal for unlocking the corresponding thyristor is given, and the counting of the pulse-generator 3 by the counter 2 is stopped. Since the code at the output of counter 2, at which the unlocking signal of the thyristor is selected, is proportional to the period of the mains supply, the time during which this code is counted at the Constant control signal at the input of the generator 3 is also proportional to the period of the mains supply; and the phase angle of thyristor control remains unchanged. Counter b counts the high-frequency output pulses of the synchronization unit 5. When the code at the output; 1e of the counter 6 corresponds to the maximum permissible value of the thyristor control phase angle at all inputs of the AND-HE 13 logic element connected to the corresponding bit outputs of the counter b, the signals of the logical unit appear. At the output of the NAND 13 element, a logical zero signal appears, which through the AND 12 element sets the P5 flip-flop 7 to a state similar to the state when the logical zero signal at the output of block 1 matches. Thereby, the phase steering angle is limited in magnitude. Register code 8 821cf, where 1s is the multiplication factor of the synchronization frequency. Counter code 2 Nj. (2) where t is the time corresponding to the interval from the beginning to the end of the counting of the counter 2, .. 21c f f The thyristor control pulse is generated at the instant of equality of the counter 2 code and the register code 8. The phase angle corresponding to the control pulse d ... 2T, i Formulas (3) imply that the phase angle is determined only by the frequency of the controlled oscillator fy and does not depend on the frequency of the network fj. . Since the code at the output of register 8 changes discretely with a continuous change in frequency, an error occurs in the phase angle of the unlocking of the thyristor P signal generator. The maximum deviation of the power supply period, at which the code at the output of the register 8 does not change yet, (4; where vf о is the period and frequency of the stable frequency generator 11. Then, the maximum deviation of the supply mains, while the frequency register does not change, at 1 J vt Maximum phase deviation. 4oi 2774fj.t - ± 2kf s (The number of bits of counters, register and block of coincidence is determined by the formula

(7)

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y- - "

(eight)

h - k

Thus, the proposed device provides, firstly, maintaining a predetermined phase angle of control while changing the frequency of the supply network with the required accuracy, accuracy is ensured by a set of necessary values of frequency f and coefficient K, and secondly limiting the phase angle of control by a predetermined value K to the connection scheme of the counter b and the logical element IS-NOT 13, thirdly, the organization of control of the register 8 and the counter 10 by the high-frequency output signal of the synchronization unit 5 which shortens the time it takes for block 1 to receive information about changes in the frequency of the mains supply.

Claims (1)

3. USSR copyright certificate No. 550755, cl. H 02 P 13/16, 197_7. = DEVICE FOR PULSE-PHASE CONTROL OF A THYRISTOR CONVERTER, containing a controlled oscillator, a first binary counter, the output of which is connected to the first input of the coincidence block, an I element, a synchronization block with a synchronizing output and a distributor, so that to increase stability of the phase angle of control at a variable frequency of the supply network, it is equipped with a stable frequency generator, second and third binary counters, a memory register, a time delay element, an element NON-RC trigger, and the synchronization block with an additional high-frequency output, with the output of the controlled generator connected to the counting input of the first binary counter, the synchronized output of the synchronization block connected to the inputs of the first and third binary counters and the R-input of the RS trigger, high-frequency the output of the synchronization unit is connected to the counting input of the third binary counter, to the overwrite input of the memory register and through the time delay element to the reset input of the second binary counter, the counting input of which is connected ene to output stable frequency generator, the output g Programmable secondary binary counter through a memory register connected to the second input matching unit output. which is connected to the first: input. • of the And element, the second input of which is connected to the output of the AND-NOT element, whose inputs are connected to the corresponding bit output of the third binary counter, the output of the And element is connected to the S-input of the RS flip-flop, whose inverse and direct outputs connected respectively to the input of the prohibition of counting the first counter and to the input of the control pulse distributor.