SU1038936A1 - Multiplication device - Google Patents

Abstract

1. DEVICE FOR MULTIPLICATION by author. St. No. 888109, characterized in that, in order to expand the funeional capabilities by providing multiplication of numbers in the additional code, it contains a h-bit adder and a correction generating unit, the first, second, third, fourth and fifth inputs of the correction generating unit are connected respectively to the multiplier, multiplier, multiplier sign, multiplicand sign and device operation mode inputs, the output of the correction generation unit is connected to the fourth input of the last computing unit of discharge values of the product, the output of the block and generating correction and output buffer registers, except the first .go buffer register of the second group are connected to respective inputs of h-p raef dkogo adder. € cl with co oo with co 05

Description

2, The device according to claim 1, I distinguish that the forg-correction block contains two adders, a buffer register, two triggers, with the first and second inputs of the correction block forming connected to the first and second groups of inputs of the first adder, the output of which is connected to the input of the second cyivOvsaTopa, the output of which is connected to the input of the buffer register, the output of which is the output of the correction shaping unit, the transfer outputs, the first and second adders are connected respectively to the first inputs of the first and second m riggers, outputs jDbjK are connected respectively to the transfer inputs of the first and second adders, the third input of the correction shaping unit is connected to the first input of the information reception reception of the first adder and the input of the first trigger, the fourth input of the correction shaping unit is connected to the second input of the information reception of the first adder and the enable input of receiving information of the second trigger; the fifth input of the correction unit is connected to the enable input of receiving information; the second register, the second input of the first and second triggers.

The invention relates to computer technology and can be used in the design of fast-running methods of multiplying the numbers represented in any positional number system in a pop-up code. Its application is especially effective when using large integrated circuits, in particular, in the development of high-performance ones. increase CPU and microprocessor systems.

According to the main author. St. No. 8881O9, a device for multiplying is known, containing a multiplicable register, n BbiiRic blocks; bit: 1st values of the product (n is the number of multiplicable bits), n buffer registers of the first group, and n buffer registers of the second group, the first inputs of the bit calculating blocks the values of the product are connected to the outputs of the corresponding bits of the register of the multiplicand, the second inputs - with the input of the device multiplier, the third and fourth inputs - with the outputs of the corresponding

The first and second buffer buffers of the first and second buffer registers are connected respectively to the high and low bits of the corresponding branch blocks for calculating bit values of star, the output of the first buffer register of the second group is connected to the output of the device, the fourth input of the last block for calculating bits These product values are connected to the device input of the device (.

A disadvantage of the known device is the impossibility of multiplying the numbers represented in the additional code on it, which reduces its scope.

The purpose of the invention is to expand the functionality of the device by providing the multiplication of numbers in the additional code.

The goal is achieved by the fact that the multiplying device additionally contains a n-bit adder and a correction generating unit, the first, second, third fourth and fifth inputs of the correction shaping unit being connected to the multiplier, multiplicand, multiplier sign, multiplicative sign and mode inputs operation of the device, the output of the correction shaping unit is connected to the fourth input of the last calculation unit of the bit values of the product, the output of the correction shaping generation unit and the outputs b} of the firing registers, Turning on the first buffer register of the second. The rpjTtnbi are connected by the corresponding inputs of the n-bit inputs of the n-bit adder.

In addition, the correction generation unit contains two sec; lmator, b} fer register, two triggers, the first and second inputs of the correction formating block being connected respectively to the first and second groups of inputs of the first adder, the output of which is connected to the input of the second adder, whose output is connected with the input of the buffer register. The output of which is the output of the correction formation 6noica, the transfer outputs of the first and second adders are connected respectively to the first inputs of the first and second triggers 1 whose outputs are connected respectively to the transfer inputs of the first and second adders, the third input of the correction shaping unit is connected to the first input of the information reception permission the first adder and the input of receiving the information of the first trigger, the fourth input of the correction shaping unit is connected to the second input of the receiving of information receiving the first- and adder input permitted audio reception and 14 | deformations of the second flip-flop, a fifth input correction generating unit connected to the input buffer register receiving authorization information, the second inputs of the first and second flip-flops, Fig. 1 shows the structural scheme of the multiplier; in fig. 2 correction block for the case of a binary-coded 2 -induced number system. The device for multiplying contains P-bit register 1 multiplicand, blocks 2 calculating the bit values of the product, n buffer registers the first 3 and second 4 groups, block 5 forming the correction, n-bit adder 6, inputs 7,8,9,10 , 11, respectively, multiplier, multiplier, multiplier sign, multiplier sign, device operation mode, outputs of the multiplier register 12, output 13 of the device. The correction generating unit contains the first and second adders 14 and 15, the buffer register 16, the first and second triggers 17 and 18. The blocks for calculating bit-generation combi-type generation values can be implemented, for example, using ROM or high-speed logic information converters. It may be advisable to implement these blocks in the form of an iterative network or on the basis of a multi-layered tree structure. The combination of the 1st block 2, the computation of either the bit values of the product and the i-th buffer registers 3 and 4 can be constructively implemented as a single module, implemented, for example, as a large integrated circuit. The correction shaping unit operates as follows. If the sign of the multiplicand is negative (input 10 of the signal of the log of 10 6 units), the go in each step of the device to the adder 14 through its first input is receiving information from the input 7 of the device multiplier, as well as before the device starts working the trigger 18 through the device mode input 11 (otherwise, the recording of information on these channels is blocked). Similarly, if the sign of the multiplier is negative (the logical unit signal is present at input 9), then adder 14 through its second input allows receiving information in each device operation cycle from input 8 of the multiplicable device, and also writes unit to trigger 17 at input 1 1 before the operation of the device (otherwise, the recording of information on these channels is blocked). It is proposed that the inputs 7 and 8 of the device each time enter the block 5 of the correction of 1s inverse binary digits of the multiplier and 1s of inverse binary digits of the multiplicand, for example, from the inverse outputs of triggers of the multiplier registers and multiplicated with chains of one-stroke shift by k bits ( the registers in the drawing are not shown). The entry in the buffer register 16 is made with the resolution of the signal at the input 11 of the device only in the multiplication mode of numbers in the additional code. When the device performs the multiplication in unsigned form, i.e. without characters, YO writing information to the buffer register is blocked. The buffer register performs in block 5 the role of a one-shot information delay, and therefore, in cases where this is not required, it must be replaced by a special combinational sampling scheme. So, with the help of block 5, in each cycle of operation of the device 1c binary DSPC correction (if the device multiplies the numbers in the additional code). The multiplication device works as follows. The operation of the device for multiplying numbers will be considered with reference to the binary-coded 2 -personal number system, i.e. when each bit of both a multiplier and a multiplier is a set of 1 binary digits. In the initial state, the buffer registers 3 and 4 and the buffer register 16 of the correction shaping unit are zero; trigger 17 holds a one if the sign of the multiplier is negative; In trigger 18, one ifflua is stored, if the xyozhim ego sign is restricted in register 1 of the multiplicator, the n-bit 2-personal multiplicand code is written (n k is the binary binary code of the multiplicand). In each of the first cycles of operation of the device at its input there are 7 actions parallel to the double digits, multiply π, nz rana from the side of the young bits of the bits At that, in -. block 2 calculating the bit values will produce the jTviHDxeHVie bitwise resolution to the multiplier posting to its second input from input 7 of the device, n to k binary, multiplicative digits, accessing the HG its first input from output 12 i -th 2 bit of register 1 multiplicand and gfibavlenie to 1 junior binary bits will give the pop-zsheg-os with 2 different random products through the fourth and third inputs of the block 2, respectively k min. the binary bits of the product (1 + 1-th block 2, formed in the previous clock and stored MXY.k. in (i +1) th buffer register 4 and 1c of the higher binary bits of the product. -i-th block 2, from in the previous clock and xpaifHMbix in the block register 3. After this, the k minor binary data, the output of the i-th block 2, are formed; it is written into the m-th register 4, and the k major binary bits are produced in the i-th buffer register 3. Simultaneously with the formation of the B cycle of operation of the device, the discharge is produced in blocks 2 of the device in the block 5 korreksh-gi forms k binary DIGITAL corrections, which are delayed by one clock and fed to the Device Correction Input. Recording information in buffer registers 3 and 4, in buffer register 16 to triggers 17 and 18 b ka 5 forming correction, & It is carried out under the action of the same c HtocpoHNcnyjibca. The output of 2 p 2 -batch work bits is carried out through the output of the device for y;,;; 13 c 1 bits of binary bits per cycle. Accelerated output of the product is possible for p + 1 hakt, for which it is necessary in the (n + 1) th hakg to sum the contents of the buffer registers 3,4 and 16 (except the first buffer register 4) on the adder 6. In the device for multiplying isg1ol, y An algorithm for specifying numbers in an additional code with flByKfsJ explicit corrections. Only ogmegigy should follow, that the pi signs of multiplicand and hardener are included in their highest 2 digits, then additional multiplicative and multiplier codes are used as corrective corrections in correction block 5, and the sign of the result is determined by the two highest and most significant digits significant 2-digit figures of the product. If the signs of the multiplicand and multiplier are not part of the older 2 igth digits (i.e., they do not participate directly in multiplication), then in addition, the multiplier and multiplier are used as corrections separately by adding modulo two characters of coxchangelles. The technical and economic advantages of the proposed device in comparison with the known one consist in extending its functionality by providing the multiplication of numbers in the additional code. In addition, it allows you to multiply the numbers in unsigned form, g, e. without taking into account signs that expands its area of application.

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Claims (2)

1. DEVICE FOR MULTIPLICATION by ed. St. No. 888109, characterized in that, in order to expand the functional capabilities by ensuring the multiplication of numbers in the additional code, ^. It contains an h-bit adder and a correction generation unit, the first, second, third, fourth and fifth inputs of the correction formation unit being connected respectively to inputs of the multiplier, the multiplicand, multiplier sign, the sign of the multiplicand and the mode of the device, forming correction block output is connected to a fourth input of the calculation unit bit values of the product f _d output block rmirovaniya correction and output buffer registers, except the first buffer register of the second group are connected to respective h-paaryadnogo adder inputs. the SU., „1038936> 2. The device according to π. 1, characterized in that the correction generating unit comprises two adders, a buffer register, two triggers, the first and second inputs of the correction generating unit being connected respectively to the first and second input group of the first adder, the output of which is connected to the input of the second adder, the output of which connected to the input of the buffer register, the output of which is the output of the correction forming unit, the transfer outputs * of the first and second adders are connected respectively to the first inputs of the first and second triggers, the outputs of the cat ryh are connected respectively to the transfer inputs of the first and second adders, the third input of the correction forming unit is connected to the first input of the information receiving permission of the first adder and the input of the information receiving permission of the first trigger, the fourth input of the correction forming unit is connected to the second input of the information receiving permission of the first adder and the permission input receiving information of the second trigger, the fifth input of the correction forming unit is connected to the input of the permission to receive information of the buffer register, the second the entrances! first and second triggers.