SU1032483A1 - Associative storage - Google Patents

Abstract

An ASSOCIATIVE STORAGE DEVICE containing detectors, digital comparison units, some of the inputs of which are connected to the outputs of the polling register and others to the outputs of information registers, characterized in that with increasing speed and expanding the field of application of the device by increasing the number of search criteria , an information analysis block is entered into it: digital-analog converters, logic blocks and analog blocks of comparison, the outputs of which are connected to the detector inputs, one of the inputs is connected to the output m information analysis unit, others - to the inputs information analysis unit and outputs of logic blocks whose inputs are connected to the outputs of transducers i leu-analog whose inputs are connected to outputs of the digital comparator blocks. (L | 1 N ||

Description

2 „The device according to A.1, о t | i and -, that is with each: the logical block contains an adder ,; operational amplifier, nonlinear elements and load elements, j, one of the terminals of the first load element and the nonlinear element and the input of the operational amplifier are connected to one of the terminals of the second load element, one of the terminals of the third load element is connected to another terminal of the first nonlinear element, one of the terminals of the second nonlinear element is connected to the output of the operating amplifier and another terminal of the third load element, and; the other output is to the other output of the first load element and the first input of the adder, the second input of which and the other output of the first load element are combined and are the input of the block, the output of which is.

3, the device according to claim 1, characterized in that the information analysis unit contains a group of non-linear elements and a fourth loading element, one of whose terminals is connected to the bias voltage bus, and the other output is combined with one of the non-linear elements of the group and is the output of a block whose inputs are other pins of non-linear elements of the group.

one

The invention relates to computing and can be used in storage devices.

The following associative criteria are known: devices that search in an array of numbers closest to a given one, containing a drive, a poll register, OR elements, counters, and detectors by the number of stored ones. signs, dynamic trigger ij

A disadvantage of the known device is reduced speed.

Closest to the proposed is an associative memory device comprising registers of stored features, a poll register, digital comparison circuits and detectors in which the bit outputs of each register of stored characteristics are connected to the first inputs of the corresponding digital comparison circuits, the second inputs of which are connected to the outputs of the same name Dov register survey 1 23.

The disadvantages of this device are the reduced speed and limited scope of its application (a small number of search criteria).

"The purpose of the invention is to increase the speed and expansion of the area of device name by increasing 1) the number of search criteria.

The goal is achieved by the fact that in an associative memory device containing detectors, digital comparison blocks, some of the inputs of which are connected to the outputs of the poll register, and others - to the outputs of the information registers, enter

information analysis block, digital-to-analog converters, logic blocks and analog block comparisons whose outputs are connected to

detector inputs, one of the inputs is connected to the output of the information analysis unit, others to the inputs of the block, information analysis and the outputs of logic blocks whose inputs are connected to the outputs of digital-to-analog converters whose inputs are connected to the outputs of digital comparison blocks.

In addition, each logical

5 block contains an adder, an operational amplifier, nonlinear elements and load elements, with one of the terminals of the first load element and the nonlinear element and the input of the operational amplifier connected to one of the terminals of the second load element, one of the terminals of the third load element is connected to another terminal of the first nonlinear element one of the terminals of the second nonlinear element is connected to the output of the operational amplifier and another terminal of the third load element, and the other output is connected to another terminal at the first load

element and the first input of the adder.

the second input of which and the other output of the first load element are combined and are the input of the block whose output is the output of the adder.

The information analysis block contains a group of nonlinear elements and a fourth load element, one of the conclusions of which is connected to the bus)

bias voltage and another pinJ

combined with one of the pins of the non-linear elements of the group and is the output of a block whose inputs are other pins of the non-linear elements of the group,

FIG. E shows a functional diagram of an associative memory device; in fig. 2 - functional diagram of the digital-to-analog converter; in fig. 3 and 4 are functional diagrams of the logic block and information analysis block, respectively.

The associative memory device (Fig. 1) contains information registers 1, poll register 2, digital comparison blocks 3, detectors 4, digital-to-analog converters 5, logic blocks 6, information analysis block 7, and analog comparison blocks 8.

The digital-to-analog converter 5 (Fig. 2) contains keys 9, rezi; tori 10 - has inputs 13f, ..., 11 -13 ', output 14 and is connected to buses 15 and 16. bias voltage.

When this converter 5 converts the code

:)

N - Ip.2

,

where pj is 1, O, 1, for example,

Logic block b (Fig. 3) is made in the form of a module forming circuit and contains the first 17, second 17 C and Third 17 load elements made, for example, in the form of resistors, the first 18 and second IS nonlinear elements (for example, diodes), an operational amplifier 19 and the adder 20. The information analysis unit 7 (Fig. 4) contains a group of nonlinear elements 21 (e.g., diodes) and a fourth load element 22 (e.g., a resistor) connected to the bias voltage bar 23. The block 7 thus performs the function of the minimum allocation circuit.

Ust; yd works as follows.

Denote by X :, is a stored attribute,

 X,, piU- a sign of the survey.

All signs are recorded as a position code.

 -f

Y y and y,

 )

I-

where - value of bits; aj - weights The stored features and the interrogation indication are simultaneously, with parallel codes, fed to the inputs of the respective digital comparison units 3.

 For the case of the binary code i-a, the digital comparison unit 3 has t inputs of the bits of the stored attribute, -, ...,, ....,, T inputs of the bits of the sign of polling y, ..., y, ... y ( and 3 m) m groups of three

exits. For each of the m groups of outputs, the relations

f.f j vjvx-.jAv:

0

ij --N-j fi

The variables, {ftj t, arrive at inputs 11 ,, 12j and 13, respectively; An i-ro digital-to-analog converter 5. The resistors 10, ..., lOj, 0.0, 10 are chosen such that

where R .- resistor resistance

OJ lOj; 0 R is a constant.

Accepting a bias voltage on the bus 15 + E and on the bus 16 - E, we get at the output 14 digital-to-analog converter 5 voltage

J-1 1

proportional to the difference of values, signs and Y.

Q When executing block b, as shown in FIG. 3, at its exit. Tension

U - (Uil,

5a when block 7 is executed, as shown in FIG. 4, we get voltage at its output

 and,, to the inputs of the i-ro analog block

0 8 comparisons, stresses U come in and, when they coincide, this fact is recorded in detector 4, thereby indicating the stored sign closest to the sign of the opus.

5 The table below shows how specific realities are. The orders of blocks b and 7 of the contents of register 2 in the device perform certain types of search.

0 Some types of search can be obtained by simplifying the device schema (for example, the search for the maximum or minimum can be obtained by excluding blocks 6). Respectively,

 A combination of schemes that implement these types of search can be used to obtain combined types of search, and the introduction of control circuits (settings; - get a multifunctional device.

Thus, the proposed device implements a wide range of functions of associative search {including the search for the most distant. At the same time, unlike the known devices, the search process occurs

for one cycle and the phenomenon of iterative accumulation of the difference between the stored signs and the signs of the survey, characteristic of the digital implementation, is absent, due to which the speed is increased.

The proposed device is most effective for associative search.

Minimum allocation scheme

Highlight pattern

Highlight pattern

Highlight pattern

Minimum allocation scheme

Minimum allocation scheme

1l

Of

ka in arrays of small dimension. In particular, it can be used as a block of specialized computer equipment, for example, a random number generator with controlled correlation, in which it is necessary to search for the nearest one in the array.

Closest to Y

Most distant from Y

The nearest smaller to

No

2 - 1 Maximum

Closest bigger y to y

Minimum

tfn§

fie.Z

but

./g/

} s25 fieL

Claims (3)

An ASSOCIATIVE MEMORY DEVICE containing detectors, digital comparison units, some of whose inputs are connected to the outputs of the polling register, and others to the outputs of the information registers, characterized in that, in order to increase the speed and expand the scope of the device by increasing the number of criteria search, it contains information analysis block digital-to-analog converters, logic blocks and analogue comparison blocks, the outputs of which are connected to the inputs of the detectors, one of the inputs is connected to the output b information analysis unit, others with inputs of the information analysis unit and outputs of logical units, the inputs of which are connected to the outputs of digital-to-analog converters, the inputs of which are connected to the outputs of digital comparison units. ’-Ns 2. The device according to claim 1, with the fact that each logical unit contains an adder, · operational amplifier, non-linear? elements and load elements, j 'and one of the terminals of the first load element and the nonlinear element and the input of the operational amplifier are connected to one of the terminals of the second load element, one of the terminals of the third load element is connected to the other terminal of the first nonlinear element, one of the terminals of the second nonlinear the element is connected to the output of the operational amplifier and another output of the third load element, and the other output to the other output of the first load element and the first input of the adder, the second input of which and the other output of the first load element are combined and are the input of the unit, the output of which is the output of the adder. 3, device pop. 1, characterized in that the information analysis unit contains a group of non-linear elements and a fourth load element, one of the terminals of which is connected to a bias voltage bus, and the other terminal is combined with one of the outputs of the non-linear elements of the group and is the output of the block whose inputs are 'other conclusions of nonlinear elements of the group.