SU1029324A1 - Device for compensating reactive power - Google Patents

Description

The invention relates to electrical engineering, in particular, to devices for automatic control of the reactive power of electrical networks using cosine capacitor batteries.

A power factor automatic regulator is known that contains a measuring element whose inputs are connected to the outputs of a current transformer and a voltage transformer, and the outputs of a measuring element are connected to a logic unit that includes the Zoom and Reduce channels, as well as a threshold element, And circuit and a switch with the number of outputs equal to the number of switchable sections of capacitor banks 1.

The disadvantage of this regulator is that the monitored parameter of the supply network (for example, reactive power, ratio, reactive load current, etc.) is measured in a suitable network phase, which leads to significant errors, under conditions of asymmetry of the supply network , since the power and nature of the loads connected to different phases of the network are different.

It is also known a device for automatic power level control, which can be used under asymmetry conditions, comprising double-faced meters connected to a switching unit of a capacitor unit, an OR circuit, a frequency divider and three single-phase control channels, each of which includes a current transformer, a capacitive voltage divider. , key amplitude limiters, AND-NOT logic circuits, inverters, pulse selectors by duration, reversible binary counter. Due to the fact that the monitored parameter is measured across all phases of the supply network, this regulator can compensate reactive power with sufficient accuracy under conditions of asymmetry G 2}.

However, the required accuracy is provided only in four-wire networks. In three-wire networks, such a device cannot provide optimal compensation of reactive power with the required accuracy, since in it the phase angle is chosen as a controllable parameter, which leads to additional p. Errors, due to the fact that the phase angle does not give information about the power loads and additional devices are required to determine the required power of the compensating stage.

The closest in technical essence to the present invention is a power factor controller containing a power factor sensor, capacitor battery section with switching blocks, the control circuits of which are connected to the outputs of the control signal drivers of the logic unit equipped with reversible binary counters, coincidence circuits and the master oscillator. In this controller, the phase shift between current and voltage is measured in a single phase, for example, A, assuming that the load of the three-phase network is symmetrical Gz.

However, it is known that even with purely active asymmetrical openings, the phase shifts between currents and voltages in different phases of the network are unequal and can have both inductive and capacitive character. Therefore, controlling the power factor control device in a single phase results in large control error. At the same time, the balance of reactive power deteriorates significantly, since the direction of regulation may be opposite to that required, which increases the loss of electrical energy in networks and reduces the transmission capacity of the line and transformers.

The purpose of the invention is to reduce electrical energy losses in networks and to increase the capacity of lines and transformers under conditions of unbalanced loads by increasing the accuracy of reactive power compensation.

This goal is achieved by the fact that in a device for compensating reactive power, containing h sections of capacitor batteries connected to the network through switching units, a reactive power sensor and a logic unit, including a master oscillator, a reversible binary counter, a coincidence circuit, and control signal formers, whose outputs connected to the control unit of the switching unit, the reactive power sensor is equipped with two voltage transformers, two current transformers, two phase-shifting units, two smart the analog signals and the summing unit; 1 logic unit is equipped with two threshold elements, an inverter, a mismatch circuit, a time delay element, a direct counting limiting circuit, a counting limiting circuit, a decoder and a mode switch, and the first and second voltage transformers

included in the forward order phase alternation, respectively, between the first and second, second and third phases of the network, and the first and second current transformers are included in the first and third phases of the network output of voltage transformers, respectively, through phase-shifting blocks connected to the first analog inputs of the multipliers of analog signals, and the outputs of the current transformers are connected to the second similar inputs of the above-mentioned multipliers, the outputs of which through the summing unit are connected to the inputs of the threshold elements of the logic unit, the output the first threshold element is connected to the input of the mismatch circuit and to the addition bus of the reversible binary counter; the output of the second threshold element is connected via an inverter to the subtraction bus of the counter and the second input of the mismatch circuit, whose output is via the time delay element to the other the input of which is connected to the output of the master oscillator, the output of the coincidence circuit is connected to the synchronous input of the reverse binary counter, the outputs of which through the forward and reverse limiting circuits with The pair is connected respectively to the inhibit and inhibit inputs of the reversing binary counter, the outputs of which are connected to the input, the operating mode switch and the decoder, and the outputs of the decoder are connected to other inputs of the switch, one input which is connected to the capacitor battery turn-on signals , and others - with form-. A tripping signal for the mentioned sections.

FIG. 1 shows the functional scheme of the device for reactive power compensation; on . 2 - timing charts for s, the operation of the device.

FIG. 1 shows M sections of capacitor batteries 1.1, 1.2, .. 1.P, switching units 2.1, 2.2, ..., 2.p switching, connecting sections of batteries to the phases of the network transformers 3, 3.1 voltage, transformers 4, 4 current, phase shifting blocks 5, 5.1, multipliers 6, 6.1 of the angled signals, summing block 7, threshold elements 8, 8.1, circuit 9 inconsistent faults, inverter 10, time delay element 11, circuit 12, match generator 13, reversible counter 14, circuit 15 forward counting restrictions, counting restriction circuit 16, descrambler 17, work sort switch 18, driver 19 signals of switching-on sections of capacitor banks, shaper 20 signals of disconnection of sections.

Elements 3, 3.1, 4, 4.1, 5., 5.1, 5 6, 6.1 and 7 form the reactive power sensor 21, and elements 8, 8.1, 9-20, are included in the logical one. block 22.

The device works in the following 10 ways.

Suppose that in its initial state the network mode is such that all sections of capacitor batteries are disabled. At the same time from the first transformer 3

15, the voltage is removed, proportional to the linear voltage of the network, and from transformer 3.1, the signal is proportional to the voltage (Fig. 1). These signals by phase-shifting blocks 5 and 5.1 are shifted by an angle equal to 90 el. Degrees. And the first analog inputs of the multipliers of analog signals b and 6.1 are fed to the other inputs of which the signals are proportional to the currents, respectively, from the transformer 4-line current, and from transformer 4.1 -. Signals proportional to the products of these quantities from the outputs

The 30 multipliers 6 and 6.1 are fed to the inputs of the summing unit 7, where they are added. At the same time, at the output of block 7 there is a signal, the constant component of which is

35 is proportional to the reactive power of the three-phase supply network. This signal is fed to the inputs of the threshold elements 8 and 8.1, and the trigger voltage of the threshold element 8 is selected greater than the threshold of the trigger threshold of the element 8.1. Suppose the constant value is the output voltage of summing unit 7, proportional to the reactive power

45 of a three-phase network at the moment of connecting the device to the network (Fig. 2, output 7) tj, less than the voltage of the response thresholds and 11.2 .threshold elements 8 and 8.1. In this case, the elements 8 5 and 8.1 are in the disconnected state and their outputs have the same, for example, low potentials (Fig. 2, O. 8 and 8.4). Low and high potentials will be present at the inputs of circuit 9, which implements the logical function EXCLUSIVE OR, since the low potential from the threshold element 8.1 is fed to the input of the 9. mismatch circuit through inverter 10 (Fig. 1 and Fig. 2). The mismatch circuit 9 is triggered and the signal from it starts the time delay element 11. On the basis of the required output (time

FIG. 2) the signal from the output cxeivu C

65 H enters one of the entrances; Matching circuits 12, to the other input of which from the master oscillator 13 there are continuously received start-up pulses of the reversing counter 14 (FIG. 2, outg. 13). The signal from the output of circuit 11 is permitting for the passage of pulses of the master oscillator 13 through circuit 12 to match the input of the reversible counter 14 (FIG. 2, output 12). At the same time, on the addition bus + of the counter 14 there will be a low potential prohibiting account and on the subtraction bus — a high potential resolving from the output of the inverter 10. Counter 14 is prepared for operation in the subtraction mode, however, due to the fact that zeros were written to the network; from the output of the counting circuit 16, the counter prohibiting the operation of the counter in the subtraction mode low potential is removed (Fig. 2, output 16). The counter is in the inhibited state, the control signals of blocks 19 and 20 are not formed and no switching occurs in the device. Suppose that at times tg (Fig. 2), the signal from the output of cooler 7, which characterizes the reactive power of the network, exceeds the voltage of the small threshold Ufj, element 8.1. In this case, the threshold element is triggered and at its output the low potential abruptly changes to high (Fig. 2, - OUT 8.1). This signal is inverted by the circuit 10 and is fed to the input of the mismatch circuit 9 and the subtraction bus of the counter 14. Then, at the inputs of the mismatch circuit 5 there will be two low potentials (Fig. 2, OUT 8 and 10, time t ,,) and the signal The output of circuit 9 is absent, circuit 11 of the time delay does not work. The enable signal does not arrive at the input of circuit 12 and the pulses from generator 13 do not pass to the start of counter 14. Control inputs of counter 14 will also have inhibitory potentials and counter. does not produce. Let at a time t the constant component of the output of the adder 7 exceed the triggering threshold Up2 of element 8. Then the low potential at its output abruptly changes to high, and at the output of element 8.1 it will still be high potential (Fig. 2, output 8, time t). In this case, at the inputs of the circuit 9, the mismatch has different potentials, it works (Fig. 2, o, 9, time t) and starts the time delay circuit 11, which is after the required hold. necessary to avoid device reactions to short-term fluctuations in the reactive power of the network, generates a signal t enabling for circuit 12 (Fig. 2, output 11) moment t). The signals from the master oscillator 13 through the circuit 12 are fed to the input of the counter 14, on the control inputs of which there are resolving the account in the add mode high potentials from the outputs of the circuits 8 and 15 (Fig. 2), the counter is inactive in the add mode (direct account ) and at its outputs high potentials l, corresponding to the voltage of the logical unit, begin to appear, according to binary code 1-2-4 ..., which are fed to the inputs of the decoder 17 and the operation mode switch 18, as well as to the circuits 15 and 16 account restrictions. From the output of the decoder 17, the signals are converted from binary code 1-2-4 ... to code 1-1-1. Consequently, the inputs of the switch 18 have signals in both the binary code fc of the outputs of the counter 14, and in the unit code (from the outputs of the decoder). Suppose that the mode of the device is selected in a single code 1-1-1. Then the signals from the decoder 17 through the switch 18 are fed to the input of the switch-on signal generator of sections (in the case of counter 14 operation in addition mode) J or to the input of the signal generator of disconnection of capacitor battery sections (in case of counter 14 operation in subtraction mode). In particular, at the time t, the pulse from the master oscillator 13 translates the first discharge of the counter 14 into a single state. When this signal is formed, a signal is also generated at the first output of the decoder 17, which, via the operation switch 18, is fed to the input of the imaging unit 19, the output of which from the first output goes to the control unit input of the switching unit 2, which connects the first section of the capacitor batteries 1 to the network (Fig 2, out 19). Simultaneously at time tg. the prohibition of the operation of the counter in the subtraction mode (Fig. 2, -;: output 16) is lifted and the signal from the output of the adder 7 is reduced by an amount, ng is the unit power of the switched on compensating stage 1. Let the power of the first section of the capacitor batteries be insufficient to compensate power network. In this case, the state of the threshold circuit elements does not change and the next impulse of the master oscillator 13 at time t.

enters the start of counter 14. A single signal is now formed at its second output and through these circuits enters the input of the switching unit of the second section, connecting it to the network. Suppose the power of the second stage is sufficient to compensate for the reactive power of the network. In this case, the signal from the output of the adder 7 becomes less than the voltage of the response threshold of the element 8 (Fig. 2, output 7 and 8), and the latter returns to the initial state. There are no mismatch signals at CX9, time delay circuit 11 returns to its initial state and signals of the master oscillator do not arrive at the synchronous input of counter 14. In addition, the addition potential of the output of threshold element 8 appears on the addition bus + counter 14 (. Fig. 2, time t).

Suppose that the deficit of the reactive power of the network continues to increase and at the moment of time t (the signal characterizing the reactive power of the network exceeds the response threshold of element 8. At the same time, the processes in the circuit will be similar to the given one. At time tA, at the output The time delay circuit ijp is the enabling signal and the pulse from the master oscillator 13 in the timeout tz is fed to the input of the counter 14. At the same time, the single signals on the first and second outputs of the counter, as well as on the third output of the decoder. the output of the decoder enters the start of the imager 19, the output of which includes the switching unit of the third section, connect it to the network (Fig. 2, time tj);

the signal from the output of the adder 7 is reduced. Suppose it becomes less than the response threshold of the element 8. The latter returns to the initial state and the counter cancels the counting of pulses in the addition mode. At the same time, the information recorded in the counter is saved until the next cycle of operation.

Let at the moment of time, the signal characterizing the reactive power decrease below the threshold U of element 8. At the same time, similar processes occur in the circuit and after the necessary time delay has been developed, counter 14 begins to work in the subtraction mode until the network’s reactive power deficit will not be reduced to the required level

In this case, at the moments of time of the tjQ, C4 circuit, three trip signals are generated from the outputs of the circuits 20, which are fed to the switching units of the sections (Fig. 2). In this case, the previously included sections are sequentially disabled and the circuit will be prepared. For the next work cycles.

The use of additional elements and circuits in this device, which allow determining at each moment of time the reactive power of the three-phase network as a whole, and not just one of its phases, and control according to this signal, ensures high accuracy of reactive power compensation under asymmetry. This reduces power losses, increases the capacity of lines and transformers,

Q The maximum power factor values are achieved and the overall performance of the power supply systems is improved overall.

Claims (1)

(54) (57) DEVICE FOR COMPENSATION OF REACTIVE POWER ·, containing AND sections of capacitor banks connected to the network through blocks. switching, a reactive power sensor, and a logic block including a master oscillator, a reversible binary counter, a matching and generating control signals circuit whose outputs are connected to the control units of the switching blocks, which means that, in order to reduce electrical losses energy in networks and increasing the throughput of lines and transformers by increasing the accuracy of reactive power compensation, the reactive power sensor is equipped with two voltage transformers, two current transformers Two phase-shifting units, two multipliers analog · signals and summing unit, a logic unit is provided with two threshold elements, the inverter circuit mismatch, an element time delay, circuit constraints directly and circuitry down count limitations deshyfratorom and operation mode switch L being. the first and second voltage transformers are connected in a direct phase sequence, respectively; the first and second, second and third phases of the network, and the first and second current transformers are included in the first and third phases of the Feti, respectively, ^ the outputs of the voltage transformers through the phaelectric shifting units are connected to the first inputs of the same name of the multipliers of analog signals, and the outputs of the current transformers are connected to the second inputs of the same name of the mentioned multipliers, the outputs of which are connected through the summing unit to the inputs of the threshold output elements of the logic block, the output of the first threshold element is connected to the input of the mismatch circuit and to the addition bus of the reversible binary counter, the output of the second threshold element through the inverter is connected to the subtraction bus of the mentioned counter and the second input of the mismatch circuit, the output of which is connected to the input through the time delay element coincidence circuit, to the other input of which the output of the master oscillator is connected, the output of the coincidence circuit is connected to the reverse sync input. a binary counter, which outputs through a circuit limiting forward and reverse bills are respectively connected to the inputs of addition prohibition and prohibition subtracting reversible binary counter, you are a _(passages which are connected to inputs of the operation mode switch, and a decoder, the decoder outputs are connected to the other inputs of said switch, one the outputs of which are connected to the shaper of switching on sections of capacitor banks, and the others are connected to a shaper of switching signals of said sections.