SU1027727A1 - Priority device - Google Patents

Abstract

1. A PRIORITY DEVICE, containing a permit generation unit, whose information inputs are request inputs, devices, and outputs are device permission outputs, characterized in that, to improve functionality by increasing the number of processing modes and adapting to the input request flow, the device contains a request analysis block, a memory block, the permission generation block contains a group of matrixes of logical blocks (where 2 is the number of information inputs of the device, an is any integer Mi a layer) consisting of n subgroups, the j-subgroup includes JB se. matrices of dimension 2, where j p, n-1, 2, 1, the outputs of the rows of the matrix of the i-th subgroup, i p, where n 1,2, are connected to the inputs of the rows and columns of the matrices

Description

And to the input of the first inverter, the output of which is connected to the second input of the first element AND, the control input of the logic unit is connected to the third input of the second element AND, the outputs of the first and second elements AND are connected to the inputs of the second OR element, the output of which is the first the information output of the logic block and through the second inverter is connected to the first input of the third element AND, the output of which is the second information output of the logic block, the output of the first element OR is connected to the second input of the third LementY3, Device under item 1, that is, that the query analysis block contains a group of counters and a group of OR elements whose outputs are connected to the counting inputs of the corresponding counters, the first inputs of all OR elements are combined and connected to the synchronization input of the query analysis block The outputs of the higher bits of the counters are connected to the second inputs of the corresponding OR elements and are the outputs of the query analysis block, the inputs for setting the zero counters are the inputs of the query analysis block.

The invention relates to digital computing and can be used in computing systems containing several active sources of information connected to a shared device, such as shared memory. A priority device is known that contains a query storage unit, a mask storage unit, a priority block, a group of elements AND, the group of inputs of the query storage block is in the first group of inputs of the device, and the group of outputs of the query storage block is connected to the first group of inputs of the priority block, the group of inputs of the mask storage unit is the second group of inputs of the device l}. The drawback of the device is the complexity and complete disconnection of low-priority channels when processing group requests of high-priority channels. The closest in technical essence to the present invention is a multichannel priority device containing decision blocking, whose information inputs are the device's request inputs, and the outputs are permission outputs, the control inputs of the permission generation unit are control inputs device, the permissions block contains logical blocks. Logical blocks in the device are connected in the form of a pyramidal structure. If the device contains 2 request inputs, then the number of possible ways to set priorities between channels is 2 (2n - i; (, 2 ...) C2. This number, however, does not provide complete freedom in setting priorities, which requires (2 ) / methods of setting, corresponding to all possible permutations of input channel numbers. The limited ability to control priorities determines a rather narrow area of application for the device. In addition, the lack of hardware for analyzing the flow of input requests makes it difficult for the device to adapt to this Thus, the device has the disadvantage of limited functionality. The purpose of the invention is to expand the functionality of the device by increasing the number of processing modes and adapting the device to the input request flow. The goal is achieved by including the permit unit The informational inputs of which are the device's request inputs, and the outputs are the device permission outputs, the query analysis and memory block, than, the resolution generation block contains r a group of matrixes of logical blocks (where 2 is the number of information inputs of the device, an is any integer number) consisting of n subgroups, j is a subgroup that includes 2 matrices of dimension, where j p, n -1,2,1, the outputs of the rows of the matrix of the i-th subgroup, i p, where p-1,2, are connected to the inputs of the rows and columns of the matrices {| -1) -th subgroup, the inputs of the rows and columns of the matrix of the n-th subgroup are the information inputs of the permit generation unit; the outputs of the rows and columns of the matrices of the first subgroup are the outputs of the form block The permissions, the control inputs of all matrices are the control inputs of the resolution generation block, the jth subgroup matrix contains logical blocks, the first inputs of logical blocks of the first row are inputs of matrix columns, the second inputs of the first column logical blocks matrix row inputs, the first inputs of the logical blocks of the last row are the outputs of the matrix columns, the second outputs of the logical blocks of the last column are the outputs of the matrix strikes, the first and second inputs of the rest ohmic blocks are connected respectively with the first output of the logical block of the same column of the previous row and with the second output of the logical block of the same row of the previous column, the group of inputs of the query analysis block is connected to the group of information inputs of the device, the group of outputs of the block. the memory outputs of which are connected to the control inputs of the permit generation unit, the clock input of the device is connected to the clock input of the query analysis block. The logic block contains three AND elements, two OR elements and two inverters, the first input of the logic block is connected to the first input of the first AND element, to the first input of the second AND element, and to the first input of the first OR element, the second input of the logic block is connected to the second input The first element OR to the second input of the second element AND to the input of the first inverter, the output of which is connected to the 10 second input of the first element AND, the control input of the logic unit is connected to the third input of the second element AND, the outputs of the first and second elements And are connected to the inputs of the second OR element, the output of which is the first information output of the logic unit and through the second inverter connected to the first input of the third element AND whose output is the second information output of the logical block, the output of the first element OR is connected to the second input of the third element I. The query analysis block contains a group of counters and a group of OR elements whose outputs are connected to the counting inputs of the corresponding counters, the first inputs of all OR elements are combined and connected The inputs with the sync input of the query analysis block, the outputs of the higher bits of the counters are connected to the second inputs of the corresponding OR elements and are the outputs of the query analysis block, the inputs for setting zero of counters are the inputs of the query analysis block. FIG. 1 shows the functional scheme of the device; in fig. 2 the same, the permit generation unit; in fig. 3 is the same logical unit; in fig. C - the same block query analysis; in fig. 5 and 6 are mnemonic diagrams explaining the principle of operation of the device. The device (Fig. 1) contains the permit generation unit 1, the device request inputs 2, the device permission outputs 3, the request analysis block, the memory block outputs 5, the memory block 6, the block outputs 7, the device clock input 8, the permission generation block contains matrices 9-15 logical blocks, logical blocks 16, inputs 17 and 18 logic blocks, outputs 19 and 20 logic blocks, input 21 of the logic block. The lagic block (Fig. 3) contains inverters 22 and 23, AND elements, OR elements 27 and 28. The query analysis block (Fig.) Contains counters 29, OR elements 30. The functions performed by logic block 16 are defined by the table. Logic block 16 performs the function of a two-input arbiter with respect to the signals arriving at inputs 17 and 18, In the absence of conflicts between these signals, i.e. with combinations of 00, 01, and 10, they are broadcast to outputs 19 and 20 regardless of the value of the signal at control input 21 (the X symbol in the table). When a conflict is detected between the signals at inputs 6 and 7 (combination 11), the logical block prefers a particular signal depending on the value of the signal at the control input 21. Thus, at the outputs 19 and 20 of the logical block 5, the simultaneous presence of logical units is eliminated. 1 is intended to resolve conflicts between interrogation signals supplied to inputs 2 as logical units. In the absence of interrogation signals, permission signals are also absent, i.e. on all outputs 3, logical zeros are formed (see the top row of the table above). In the presence of a single potential request signal at one of the inputs of group 2, this signal passes through everything encountered in its path.

,,,

K2 - S.K6, K2-9-K7,,,,

,,,,

, К6-Ж1,, К6 - Ж4,

.,,,

,,

. logical blocks 16 and is fed to the corresponding output of the group in the form of a single potential signal. In this case, the code on the control inputs can be any (see the X character in rows 2 and 3 of the table above). If several signals of logical units are simultaneously applied to the inputs 2 of the device, then these signals, meeting each with each in the corresponding lattice sites, are subjected to selection, as a result of which only one signal reaches the outputs 3. The relationship between any pair of competing interrogation signals is uniquely determined by the control code applied to the outputs 5 (see lines 4 and 5 of the table above). Let, for example, it is required to ensure the following priority of the inputs 2 K1-K8 (numbering is shown in Fig. 1): KZ-K2-G8-K6-K7-G1-G5-G, the arrow in such a record is directed from the higher-priority input to the lower priority . To provide this mode, the control code at the outputs 5 must configure the logic blocks in the lattice nodes as follows:

Each of these conditions is determined by the value of the corresponding bit of the control code applied to the outputs 5.

Similarly, you can set any priority order between channels. The number of such modes is equal to the number of permutations between the channel numbers: Pg 40320.

However, this number does not exhaust all possible modes of operation of the device.

Indeed, since the number of control inputs is equal to this adj. Oq

If Sd 28, then 2 268 3545b tuning options are possible, which, with the exception of those previously considered, are characterized by a flexible distribution of priorities between the channels.

The meaning of these modes is that the priority between the channels is determined not only by the control code applied to the inputs of block k, but also depends on the number of incoming requests and their distribution across channels. If, in the previous example, to change the value of only one bit in the control code, namely, the bit that defines the relationship between the inputs K and K, then the condition marked with a sign previously changed to the opposite:. Such a change, as shown; below results in one of the flexible modes. Suppose that the request signals were received on all inputs K1 f K8. FIG. 5 thick lines show the propagation paths of the interrogation signals through block 1. It is clear that the interaction of signals K4 and K5 overcomes the signal at input K5, since the corresponding lattice pattern node is set to priority transmission of signal K5 when a conflict occurs between K5 and K4 () . This signal further interacts with the signal at the input of the short-circuit and this time ceases to exist, since it does not withstand competition with the signal at the input of the short-circuit (). The resulting signal from the input of the CC successively wins the signals at the inputs of KB, K7, K8, K2 and K1 and, since the node marked with the sign-jt, there is no competing signal at the input K4 ()

passes unhindered to the exit of the block.

The K2 input signal, although a higher priority in relation to the signals from the K5 Kb inputs, is not encountered blue in its path, the latter are suppressed by the signal from the Kz 1 signal, the K2 signal, passed before the signal with the Kz channel, stops

fO existence (). The input signal K1 has a relatively low priority (one out of seven shooters tend to reject the signal K1 in case of conflicts), however, it’s not

15 paths of competitors, it penetrates deep enough into the structure and ceases to exist only when it encounters a signal on the KZTak channel, with this tune of 20K lattice nodes and when all of the incoming request signals are received, a short signal will pass. However, it is not possible to conclude from this that short-circuit is the strongest. Indeed, as shown below, when requests are received not by eight, but by four inputs of К1 t КЦ, not КЗ, but К4 wins. Consider the input interaction diagram shown in FIG. 6. Signals K1 and K2, meeting with a short-circuit signal, drop out of the competitive struggle. Signal K4, not meeting resistance from the CB K8 and K2, passes to the node marked with a sign, and suspends the propagation of a short-circuit signal, because of the condition. Thus, channel K has the maximum priority, with the number of requests equal to four, and their distribution among channels according to FIG. 5. Summarizing the consideration of the operation of unit 1, the following conclusions can be made. Block 1 can be configured to work in one of 2 modes, among which there are 8 / modes of rigid assignment of priorities and (.) Flexible or democratic modes. Any of the rigid regimes is characterized by established channel subordination. The priority order is absolute, the highest priority signal always wins, the signal with the lowest priority does not have the opportunity to win in the competition with any other signal. The latter circumstance leads to the fact that low-priority channels generally do not receive service at a sufficiently high total intensity of the flow of requests on higher-priority channels.

Any of the flexible modes to some extent eliminates the disadvantage noted above. Channel priorities are no longer absolute but rather probabilistic in nature. Low-priority channels are not pushed aside by high-priority channels, but they occasionally realize chances (even if they are low) for maintenance. The high priority channels, in turn, periodically ycTy have a low priority place, since priority between channels is a function of the number and distribution of requests across channels.

Block 21 is designed to collect information about the flow of input requests. Each input 2 is assigned a service waiting time counter 29. In the absence of requests for inputs 2, zero signals are given, all counters are set, and O are set to reset inputs. When one or more of the interrogation signals arrive, the corresponding counters begin counting the service waiting times.

If the waiting time has exceeded a certain amount determined by the frequency of the signals at input 8 and the size of the corresponding counter, the time is stopped, and in the high order of the counter the unit is fixed. When the request is satisfied, the counter is reset and the process repeats further.

When the service discipline is correctly chosen, all channels, with at least some delay, receive service, with logical zeros always present at outputs 7. Otherwise, at the outputs 7, there appear single signals warning the external subscriber about the need to reorganize the priority dependencies in the direction of increasing the likelihood of serving those channels that have been in the waiting state for a long time. The restructuring of the priority structure is achieved by changing the code at the outputs 5 by selecting the appropriate code from block 6.

The application of the invention allows to expand the functionality of the device by adapting it to the input request flow.

phage

Claims (3)

1-PRIORITY DEVICE containing a permission generation unit, the information inputs of which are request inputs, devices, and the outputs are device permission outputs, characterized in that, in order to expand the functionality by increasing-. of the number of processing modes and adaptation to the input request stream, the device contains a request analysis block, a memory block, and the permission generation block contains a group of 2 ^П · ^{1 2} matrices of logical blocks (where ^2nd is the number of information inputs of the device, and η is any integer), consisting of η subgroups, the jth subgroup includes. 2 ⁿ “J matrices of dimension 2 ³ ~ ^ 2 ^J ~ ⁴ , where J = n, n-1, 2, 1, the outputs of the rows of the matrix of the ith subgroup, ί - η, where η = 1,2, are connected to inputs of rows and columns of matrices of the ("-1) th subgroup, inputs of rows and columns of the matrix of the fifth subgroup are information inputs of the permission block, outputs of rows and columns of the matrices of the first subgroup are outputs of the permission block, the group of control inputs of all matrices are a group control inputs of the permission generation block, the matrix of the jth subgroup contains 22 (; - f / logical blocks, the first inputs The logical blocks of the first row are the inputs of the matrix columns, the second inputs of the logical blocks of the first column are the inputs of the matrix rows, the first inputs .. the logical blocks of the last row are the outputs of the matrix columns, the second outputs of the logical blocks of the last column are the outputs of the matrix rows, the first and second inputs of the rest logical blocks are connected respectively with the first output of the logical block of the same column of the previous row and with the second output of the logical block of the same row of the previous column, groups input query analysis unit is connected with a group of Information vhodov'ustroystva Group request analysis unit outputs coupled to a group address inputs of memory unit, information outputs of which are connected to control inputs of the block forming device permits a clock input connected to the clock vhodombloka analysis requests. 2. The device according to π. 1, characterized in that the logic unit contains three AND elements, two OR elements and two inverters, the first input of the logical unit is connected to the first input of the first element AND, to the first input of the second AND element and to the first input of the first OR element, the second logical input block lift m m m m> is connected to the second input of the first OR element, to the second input of the second AND element and to the input of the first inverter, the output of which is connected to the second input of the first AND element, the control input of the logic unit is connected to the third input of the second AND element, the outputs of the first and second elements AND are connected with the inputs of the second OR element, the output of which is the first information output of the logical unit and connected through the second inverter to the first input of the third AND element, the output of which is the second information output of the logical lock, the output of the first element OR is connected to the second input of the third element. 3, The apparatus of claim. ^ Characterized in that the request analysis unit contains a group of counters and a group of OR elements, the outputs of which are connected to the counting inputs of the corresponding counters, the first inputs of all OR elements are combined and connected to the synchronization input of the request analysis block, outputs of the older ones the bits of the counters are connected to the second inputs of the corresponding OR elements and are the outputs of the request analysis unit, the inputs for setting the counters zero are the inputs of the request analysis unit.