SU1016841A1 - Multifunctional logic element - Google Patents

Abstract

MULTIFUNCTIONAL LOGICAL ELEMENT on MOS transistors containing the input bus of the first logical signal connected to the input of the first inverter, the input bus of the second logical signal connected to the input of the second inverter, and the input bus of the third logical signal, characterized by the fact that increasing its speed and reducing power consumption; two 11 sticks of two series-connected p-type transistors are introduced into it, the first of which is connected between the output of the first inverter and the output w another, and the second between the output of the second inverter and the output bus, and three chains of two series-connected h-type transistors connected between the output bus and the common bus, with the gates of the p-type transistors of the first chain connected respectively to the output of the second inverter and to the input the third logical signal inversion bus, the p-type transistors of the second chain transistors - to the output of the first inverter and to the input bus of the third logic signal, the gates of n-type transistors of the first chain - to inputN (L bus of the third loop) and the input bus of the first logic signal, the gates of the second-chain h-type transistors to the input bus of the third logical signal inversion and the input bus of the second logical signal, and the gates of the n-type third transistors - to the output of the first inverter and to the output of the second inverter. O) 00

Description

The invention relates to computing, electronics and automation.

A multifunctional logic element on a MIS transistor is known, which contains the first and second equivalence elements, in which the inputs are connected to information and control buses, and the outputs are via aJfeMeH AND connected to the input of the third equivalence element, the second input of which is connected to the corresponding control bus l.

The disadvantages of this element are low speed and high power consumption.

Also known is a multifunctional logic element on MIS transistors containing the input bus of the first logic signal connected to the input of the first inverter, the input bus of the second logical signal connected to the input of the second inverter, the input bus of the third logical signal connected to the equivalence element, and the output amplifier. A distinctive feature of this element is that it contains three series-connected cascades performed on p-type 2J MOSFET transistors.

The disadvantages of this element are low speed and high power consumption.

The purpose of the invention is to increase speed and reduce power consumption.

The goal is achieved by the fact that the multifunctional logic element on the VDP transistors containing the input bus of the first logical signal connected to the input of the first inverter, the input bus of the second logical signal connected to the input of the second inverter, and the input bus of the third logical signal are entered from two series-connected p-type transistors, the first of which is connected between the output of the first inverter and the output bus, and the second between the output of the second inverter and the output bus, and three chains of two series-type n-type transistors connected between the output bus and the common bus, the gates of p-type transistors of the first chain are connected, respectively, to the output of the second inverter and to the input bus of the inversion of the third logic signal, gates of p-type transistors of the second chain - to the output of the first inverter and to the input bus of the third logical signal, gates of n-type transistors of the first chain - to the input bus of the third logical signal and to the input bus of the third logical signal and to the input oh bus of the first logic signal, gates of n-type transistors of the second chain — to the inversion input bus of the third logic signal and to the input bus of the second logic signal, and the output voltage of the third inverter and to the output second inverter.

The drawing shows an electrical schematic diagram of the proposed element.

The element contains the input bus 1 of the first logic signal A, under (connected to the input of the first inverter (On MIS transistors 2 and 3 of an additional type connected between the power bus 4 and the common bus 5. The input b of the second logic signal B is connected to the input of the second an inverter made on MOSFET 7 and 8 is additionally of the same type.The first chain of two - series-connected transistors 10 and 11 is connected between the output of the first inverter and the output bus 9. The second circuit is connected between the output of the second inverter and the output bus. The package consists of two p-type transistors 12 and 13. Three lines are connected between buses 9 and 5, each of which contains two transistors 14 and 15.16 and 17 and 18 and 19 | 1-types connected in series. 3 and 15 are connected to bus 1, and the gates of transistors 7.8 and 11 to bus 6 To bus 20 of the third logic signal C, the gates of transistors 13 and 14 are connected, and to bus 21 of the inversion of the third logic signal C the gates of transistors 11 and 16 .

The output of the first inverter, formed by the drains of transistors 2 and 3, is connected to the gates of transistors 12 and 18, and the output of the second inverter, formed by the drains of transistors 7 and 8, to the gates of transistors 10 and 1

The operation of the logic element is illustrated using Tables 1 and 2.

Table 1 shows the numbers of the control signal sets in the first column. In the next three columns, the values of the first, second and third logic signals are given, respectively, in the last column the functions implemented at the output of the element.

Table 1

one

9

one

ABOUT

Xi

ABOUT

X,

Table 2 illustrates the implementation of the function

F

at the output of the element on the first set of logical signals table.1.

Table 2 in the first column shows the numbers of the sets of logical signals.

Conductive transistors

0O -1,4,6,9,11,12

1Q Q 11,3,4,7,11,12

2O 1 O1,2,6,9,10,11,14

30111,2,3,7,10,11,14

Similarly, we can consider the implementation of all the functions of the element listed in Table 1.

The use of an inverter at the output also allows one to obtain additions to these functions. Thus, the element

one

Xj

about 1

one

one.

x „

X.X

cash. In the next three columns, the values of the first, second, and third logic signals are given, respectively, in the fifth and sixth columns, respectively, the numbers of the conductive and closed transistors, in the last column the function value at the output of the element.

Table 2

Closed transistors

2,3,5,7,8,10,13,14 2,5,6,8,9,10,13,14 3,4,5,7,8, -12,13 4,5,6, 8,9,12,13

implements all logical functions of two variables.

Since the speed of the element depends on the time of recharging the output capacitances through a chain of successively included transistors.

then, due to the smaller number of cascades on which the proposed element is implemented, its lice performance is 1.4 times as compared with the known one. Below are the results of speed comparison when switching the input logically 5, .. signals from 1 e O and from o. in 1 known and proposed multifunctional elements obtained on a computer.

Tj, offer

famous

EA element, not.

element not

97 52 78

52

Due to the fact that the multifunctional logic element is implemented on MIS transistors of the additional -wero type, the power consumption is reduced in comparison with the known elements made on p-type Mfllttrnzistors.

Claims (1)

MULTI-FUNCTIONAL LOGIC ELEMENT on MOS transistors, containing the input bus of the first logical signal connected to the input of the first inverter, the input bus of the second logical signal connected to the input of the second inverter, and the input bus of the third logical signal, distinguishing it by the fact that in order to increase its speed and reduce power consumption, two chains of two p-type transistors connected in series were introduced into it, the first of which is connected between the output of the first inverter and the output bus, and the second is between the output of the second inverter and the output bus, and three chains of two series-connected p-type transistors connected between the output 'bus and the common bus, and the gates of the p-type transistors of the first circuit are connected respectively to the output of the second inverter and to the input inversion bus third logical signal, gates of p-type transistors. a second chain - to the output of the first inverter and to a third input bus _β logic signal, the gates traneis-® tori η-type first chain - to ^Rin ° D1l xk hydrochloric bus The signal of the third logical] F / 1 Nala input bus and to the first logic of the signal, the gates of the h-type transistors of the second circuit to the input · inversion bus of the third logical AND signal and to the input bus of the second logical signal, and the gates of the η-type transistors of the third chain to the output of the first inverter and the output of the second inverter . ABOUT