SU1012445A1 - Digital adaptive corrector of multiple phase modulation signals - Google Patents

Description

The output of the third additional multiplier is connected to the second inputs of the first and second multipliers: the output of the fourth additional multiplier is connected to the second inputs of the third and fourth multipliers of each control unit. And the outputs of the summators of the in-phase and quadrature subchannels are equalizer outputs.

The invention relates to telecommunications and can be used in digital adaptive receivers of discrete signals operating at a transmission rate of 2400 bps and 4200 bps.

A device for adaptive correction of multiple phase modulation signals is known, containing an analog delay line with taps, in-phase and quadrature gain controllers, an error detection unit, sine and cosine transducers Cl 3B, this device produces signals for adjusting the offset gain factors by comparing the received-element module signal with a constant reference module, so that the convergence of the adaptation algorithm does not depend | on the likelihood of error in the decision block.

The disadvantage of this device is the presence of analog elements, which significantly limits its scope. about

A digital adaptive multi-phase modulation signal equalizer is known, consisting of an in-phase subchannel filter and a quadrature subchannel filter, of which contains a delay line with N taps of in-phase and square attenuators and an adder, and M control blocks, each of which contains four multipliers and two an adder wherein the output of the first multiplier is connected to the first input of the first adder, the second input of which is connected to the output of the fourth multiplier, the output of the second multiplier is connected to the first the second adder's input, the second input of which is connected to the third multiplier; the input taps of the delay lines are equalizer inputs; the taps of the in-phase subchannel filter delay lines through the in-phase attenuators are connected to the first input of the in-phase subchannel filter adder, and through the quadrature attenuators are connected to the first input adder filter quadrature subchannel, taps the delay line of the filter quadrature subchannel through in-phase

: attenuators are connected to the second input of the quadrature subchannel filter adder, and via quadrature attenuators are connected to the second input of the common-mode subchannel filter adder, each tap of the depletion line of the common-mode subchannel filter is connected to the first inputs of the first and third multipliers, and each withdrawal of the delay line of the quadrature subchannel filter is from the first inputs of the second and fourth multipliers of the corresponding control unit, the output of the first adder of which is connected to the second input of the corresponding terminal aznogo attenuator-phase subchannel filter and a second input of the respective phase quadrature attenuator subchannel filter and a second adder connected to a second input of the respective filter the quadrature-phase sub-channel attenuator and the second input of a respective attenuator quadrature filter quadrature subchannel 2}. .

A disadvantage of the known digital adapted equalizer is that at the beginning of a communication session, when the parameters of the corrector are very different from the optimal ones, this advertising corrector may not be adjusted due to the high probability of making a correct decision error.

The purpose of the invention is to improve the accuracy of adjusting the offset while increasing the probability of error and frequency shift in the communication channel.

To achieve this goal, a digital adaptive multi-phase modulation signal equalizer consisting of an in-phase subchannel filter and a quadrature subchannel filter, each of which contains a delay line with N taps, an in-phase and quadrature attractor and an adder, and N control blocks, ka one of which contains four multipliers and two adders, with the output of the first multiplier connected to the first input of the first adder, the second input of which is connected to the output of the fourth multiplier, the output of the second The multiplier is connected to the first input of the second adder, the second input of which is connected to the output of the third multiplier; connected to the first input of the adder filter, quadrature. Subchannel line taps. : the delays of the quadrature subr-ala filter through the in-phase attenuators i are connected to the second input of the summator of the quadrature subchannel filter, and through the quadrature attenuators - to the second input of the adder of the CHN filter of the phase subchannel, each tap; the delay line of the in-phase subchannel filter is connected to the first inputs of the first and third multipliers, and each tap of the delay line of the quadrature subchannel filter is,. with the first inputs of the second and fourth multipliers of the corresponding development unit, the output of the first adder of which is connected to the second input of the corresponding common-mode in-channel subchannel filter attenuator and the second input of its corresponding in-phase quadrant subchannel filter amplifier, .a output of the second adder of the co- channel. dinene with the second input of the corresponding quadrature attenuator of the in-phase subchannel filter and the second input of the corresponding quadrature regional attenuator of the quadrature subchannel filter, four additional multipliers, an additional adder and a subtractor are entered, with the inputs of the first additional multiplier and one of the inputs of the third additional multiplier connected to the output of the common-mode subchannel filter adder, the inputs of the second additional multiplier and one of the fourth inputs complements the output of the first additional multiplier is connected to the first input of the additional adder, the second input of which is connected to the output of the second additional multiplier, the output of the additional adder is connected to the input of the subtracter, the output of which is connected to the other inputs of the third and the fourth additional multipliers, the output of the third additional multiplier Connected to the second inputs of the first | and second multipliers, Exit fourth supplementary peremnozkitel connected to second inputs of

the third and fourth multipliers of each unit are controlled, and the outputs of the in-phase filter adders. J quadrature subchannels are outputs of a digital adaptive equalizer.

Such an implementation ensures that pac-j extends the limits of tuning of the digital adaptive equalizer regardless of the error probability and the frequency shift-0 in the communication channel, since in this case the output is produced by signals generated by comparing the received signal modulus with a constant reference module.

The drawing shows a structural electrical circuit of a digital adaptive equalizer of signals of multiple digital modulation.

The digital adaptive multi-phase modulation signal equalizer contains filters of 1, 2 in-phase and quadrature subchannels. Filter I of the in-phase subchannel contains a delay line 3 — each of N taps is connected to the input of one of the N common-mode attenuators 4–4 and to the input of one of the N. quadrature attenuators 5–5), all outputs of the in-phase attenuator 4–4 ( yj

0 connected to the input of the adder b, and the outputs of the quadrature attenuators are connected to the input of the adder. 7

Filter 2 quadrature subchannel contains a delay line 8- - 8 each of the N taps of which is connected to the input of one of the N common-mode attenuators 9, 9 | y | and to the input of one of the N quadrature attenuators 10 - 10 | c, all the outputs of the common-mode attenuators. connected to the second input of the adder 7, and the outputs of quadrature attenuators 10 - lOfyj connected to the second input of the adder 6. The output of the adder b, which is the output of the in-phase digital adaptive equalizer subchannel, is also connected to two inputs of the first additional multiplier 11, the output of which is connected to the first input additional

0 adder 12.

The output of the adder 7, which is the output of the quadrature subchannel of the digital adaptive equalizer, is connected to two inputs of the second

5, an additional multiplier 13, the output of which is connected to the second input of the additional adder 12, the output of which is connected to the first input of the subtracting unit 14, to the second input of which a reference signal AO is fed.

The output of subtraction unit 14 is connected to the first inputs of the third and fourth additional multipliers 15 and 16, with the second input of the third

5 additional multiplier 15 is connected to the output of the adder b, and the second input of the fourth additional multiplier: 5 16 is connected to the output of the adder 7. The output of the third additional multiplier 15 is connected to the first input of the first multiplier 17, and the second input of the first multiplier 1 is connected to one of the N taps of the delay line 3 - 3, the filter 1 of the synpha subchannel, and the second input of the multiplier 18 is connected to one of the N taps of the delay line 8 -, the filter 2 of the quadrature subchannel. The output of the fourth additional multiplier 16 is connected to the second inputs of the fourth multiplier 1 and the third multiplier 20, and the second input of the third multiplier 20 is connected to one of the N taps of the delay line. filter 1 in-phase subchannel, and the second input of the fourth multiplier 19 is connected to one of the N taps of the delay line 8-, filter 2 quadrature subchannel. The output of the first multiplier 17 is connected to the first input of the first adder 21, the second input of which is connected to the output of the fourth multiplier 19. The output of the first adder 21 is connected to the second input of one of the N common-mode attenuators 4. - 4 | filter 1 in-phase subchannel and with the second input of one of the M in-phase attenuators 9 - 9j filter 2 quadrature subchannel. The output of the third multiplier 20 is connected to the first input of the second adder 22, the second input of which is connected to the output of the second multiplier 18. The output of the second adder 22 is connected to the second input of one of the N quadrature attenuators 5 N filter 1 of the in-phase subchannel and the second input of one of the N quadrature Attenuators 10 - 10. Filter 2 quadrature subchannel. The device works as follows. The digital signal, in the form of two components, the in-phase Xg (i) and quadrature Xji (i), is fed to the inputs of the adaptive digital equalizer. The signals from the taps of the delay line 3- - Zts4 of the synaptic filter 1 under the channel through the in-phase attenuators 4-4 (fed to the input of the adder 6. By optimally selecting the parameters of the in-phase attenuators 4 4jyj, the intersymbol interference in the in-phase subchannel is compensated. compensated by applying through quadrature attenuators 10-, 10 .J a filter 2 of a quadrature subchannel to the second input of the adder b signals with a tap of the delay line 8, ", filter 2 quadrature sub Signals from the taps of the delay line 8 - 8 N of the filter 2 of the quadrature subchannel through the in-phase attenuators 9 - are fed to the input of the adder 7. The choice of optimal solutions for the pair of meters of the in-phase attenuators compensates for its own intersymbol interference in the quadrature subchannel. feeds through quadrature attenuators 5x, - 5, to the second input of the adder 7 signals with a 3–3 | h filter of the in-phase subchannel filter 3; h. The filtered two-dimensional signal SUS () CD is fed to the inputs of the decision block (not shown). Modification of the transmission coefficients of the in-phase attenuators (4) vj, 9 9ud) and quadrature attenuators (5-, - SN, 10 - lOpj) - CCN filters 1, 2 of the in-phase and quadrature subchannels are implemented using a control circuit in which signals for adjusting attenuators in accordance with the adaptation algorithm S5p (+1) Csn (i) - | u.rA (i) - A (,) -s (Kn) + Usr) X. 1-) g YcV I; Xq. I - fJi Ccn (+ 1)) - () -AO -n) + .yg (i) x. -n) j, n 0,1 ... N, where Сц (1+ 1), Cgj, (1) - the value of the transmission coefficients of the in-phase attenuators of the digital adaptive equalizer at (i + 1) -th and i-th steps of adaptation ; Cj, (i + l), Ccn (i) is the value of the transfer coefficients of the quadrature attenuators of the digital adaptive equalizer in the (i +.1) -th and i-th steps of adaptation; l2 () y | (0+) - the value of the square of the signal module at the i-th adaptation step; AQ - reference signal; a) in-phase and square-wave components of the filtered signal; xg (i -n), Xj (i - n) are the in-phase and quadrature components of the input signal on the nth tap of the delay line; fA. - constant multiplier, which determines the speed of adaptation. Such a connection of the nodes allows to obtain a digital adaptive equalizer of phase modulation signals with wider tuning limits, regardless of the frequency shift e: kangsha of the communication, which is tuned at any probability of error on the output of the decision circuit, which allows; digital adaptive corrector of phase modulation signals in signal converter devices with transmission speeds of 2400 bps, 4800 bps operating on channels of a tonal frequency of any length without preliminary. : manual settings.

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Claims (1)

DIGITAL ADAPTIVE CORRECTOR OF SIGNALS OF MULTIPLE ONE-TIME MODULATION, consisting of a common-mode subchannel filter and a quadrature subchannel filter, each of which contains a delay line with N taps, common-mode and quadrature attenuators and an adder, and of N control units, each of which contains four switches. and two adders, the output of the first ¹ multiplier connected to the first input of the first adder, the second input of which connected to the output of the fourth multiplier, the output of the second multiplier connected to the first input of the second adder, the second input of which is connected to the output of the third multiplier, and input taps' the delay lines are the inputs of the digital corrector, the taps of the delay line of the in-phase subchannel filter are connected through the in-phase attenuators to the first input of the adder of the in-phase subchannel filter, and through quadrature the attenuators are connected to the first one: the input of the adder filter of the quadrature subchannel, the taps of the delay line of the filter of the quadrature subchannel through in-phase attenuators are connected to the second input of the filter adder of the quadrature subchannel, and through the quadrature attenuators to the second input of the adder of the in-phase filter of the in-phase subchannel ·· subchannel is connected to the first inputs of the first and third multipliers, and each tap of the delay line of the filter of the quadrature subchannel is connected to the first inputs of the second о and the fourth multiplier of the corresponding control unit, the output of the first adder of which is connected to the second input of the corresponding common-mode filter attenuator of the in-phase subchannel and to the second input of the corresponding common-mode filter attenuator of the quadrature subchannel, and the output of the second adder is connected to the second input of the corresponding quadrature filter attenuator of the common-mode subchannel and to the second the input of the corresponding quadrature attenuator filter quadrature subchannel, characterized in that, in order to increase the accuracy of adjusting the corrector with increasing the probability of error and frequency shift in the communication channel, four additional multipliers, an additional adder and a subtraction unit are introduced, while the inputs of the first, additional multiplier and one of the inputs of the third additional multiplier are connected to the output * of the adder of the common-mode subchannel filter, the inputs of the second additional multiplier and one of the inputs of the fourth additional multiplier connected to the output of the adder filter quadrature subchannel output the first additional multiplier is connected to the first input of the additional adder, the second input of which is connected to the output of the second additional multiplier, the output of the additional adder is connected to the input of the subtraction unit, the output of which is connected to other inputs of the third and fourth additional multiply SU „1014455 lei, the output of the third additional multiplier is connected to the second inputs of the first and second multipliers, the output of the fourth additional multiplier is connected to the second inputs of the third and fourth multipliers of each control unit, and the outputs of the Filter adders of the common-mode and quadrature subchannels are the corrector outputs.