SU1003126A1 - Device for receiving and displaying information - Google Patents

Description

(5) DEVICE TO RECEIVE AND DISPLAY INFORMATION

The invention relates to computing and is intended for use in the input circuits of data acquisition and processing systems.

A device for receiving telemechanical information is known, comprising a distributor, a control unit, a register, a linear unit, an intermediate memory unit, a bitwise comparison unit, a pulse counter, an AND element, a generator and display elements consisting of AND elements, scaling elements and display units. til ..

The drawback of the device is the low reliability of the information conveyed to the operator, due to the fact that the newly received information is not blinking to attract the attention of the operator to this information, and also because the operator cannot quickly intervene in the information display process.

The closest in technical essence to the present invention is a device for receiving a serial code comprising a first counter, the first input of which is connected to the second clock bus by the first input of the first, second, and third AND-NOT elements, the second input is connected to the second input of the third AND-NOT element the first input of the first trigger and the input

10 of the OR element, and the output is connected to the first input of the second decoder, the second input of which is connected to the first clock bus and to the second inputs of the second and third trigger, and the output to the second input of the first trigger whose output is connected to the third input of the third element IS-NOT, the second input of the second IS-element is connected to the first informational bus, and the output is connected to the second input of the first trigger, the second input of the third AND-NOT element is connected to the second information bus, and the output to the second input of the second trigger and the first the inputs of the second count ik and the second decoder, the output of the third element IS is NOT connected to the input of the record of the shift register, and the output of the register of the shift through the code converter is connected to the first input of the memory registers, the outputs of which are connected to the inputs of the corresponding indicators and the outputs of the first and second triggers are connected respectively with the information input of the shift register and the first input of the OR element, the output of the second counter through the second spacer is connected to the second inputs of the memory registers, the second inputs of the OR element, the second counter, and the third input register Memory pads are merged and connected to the setup bus to zero 2. A disadvantage of this device is the low reliability of the information provided to the operator due to the fact that this device does not provide flicker when new information is received and therefore the operator’s attention is not drawn to the newly received information for its analysis and decision in accordance with its content. In addition, the operator cannot promptly intervene in the process of displaying information and when receiving such information, where each symbol denotes a certain concept, on a board of small volume (two to ten characters), it is possible to lose previously received and unprocessed information. The increase in the size of the scoreboard leads to the fact that the operator is very difficult to orient with in a large array of displayed characters. The purpose of the invention is to increase the reliability of information provided to the operator. The goal is achieved by the fact that the device for receiving and displaying information containing a serial code receiving unit, the first and second inputs of which are connected to the clock inputs of the device, the third and fourth inputs to the information inputs of the device, the fifth input to the input of setting to zero The first output of the sequential code block is connected to the first inputs of the first and second memory registers via a code converter, the outputs of which are connected to the first inputs of the first and second indi, respectively. counting triggers, switching triggers, low frequency generator, control buttons, AND, AND-OR, AND-NOT elements and OR element, the first input of which is connected to the device setup input, the OR element output is connected to the zero input of the first counting trigger, the direct and inverse outputs of which are connected to the first inputs of the first and second AND NAND, respectively, the second inputs of which are combined with the counting input of the first counting trigger and connected to the second output of the serial code receiving unit, the output The first element AND-NOT is connected to the second input of the first memory register, the single input of the first switching trigger and the zero input of the second counting trigger, the single output of which is connected to the first inputs of the first AND-OR element and the first AND element, the second input of the first AND element, the first the inputs of the third element AND-NOT, the second element AND-OR, and the counting input of the second counting trigger are combined and are connected to the first control button; the zero output of the second counting trigger is connected to the second input of the third AND-NOT element, output which is connected to the zero input of the first switching trigger, the output of the first switching trigger co1: G4INn with the first input of the fourth AND-NOT element and the second input of the first AND-OR element, the output of which is connected to the single input of the first counting trigger, the output of the first AND element connected to the third the input of the first memory register and the second input of the second AND-OR element, the output of the i-ioh is connected to the second input of the OR element, the output of the second element; -HT NID is connected to the second input of the SECOND memory register register, the unit of the second switching trigger and the zero input of the third counting trigger, the unit output of which is connected to the third input of the second AND-OR element and the first input of the second AND element, the output of which is connected to the third inputs the second register of the memory and the first element AND-OR, the zero output of the third countable trigger is connected to the first input of the first 5. the second NI element, the fourth input of the first AND-OR element and the counting input of the third counting switching trigger are combined and connected to the second control button, the output of the fifth AND-N element is connected to zero the input of the second switching trigger, the output of which is connected to the fourth input of the second AND-OR element and the first input of the sixth AND-NOT element, the second inputs of the Fourth and sixth elements. NAND is combined and connected to the output of the low frequency generator, the outputs of the fourth and sixth elements of the NAND are connected to the second inputs of the first and second indicators, respectively. FIG. 1 shows a functional diagram of an apparatus for receiving information; in fig. 2 - execution of the serial code reception unit. The device contains a block 1 receiving a serial code, a converter 2 codes, registers 3 and i memory, indicators 5 and 6, counting triggers 7-9, switching triggers 10 and 11, generator 12, AND-OR elements 13 and k, AND elements 15 and 1b, AND-NOT elements 17-22, OR element 23, control buttons 2 and 25, device clock inputs 2b and 27, device information inputs 28 and 29, zero input 30, outputs 31 and 32 of the sequential receive unit 1 code. The sequential code receiving unit 1 (Fig. 2 I contains counter 33, decoder 3, triggers 35-37, shift register 38, AND-NES elements, OR element +2. The device operates as follows. When power is turned on, the bus enters 30 the setting signal and the shift register 38, the counter 33, the trigger 35 of the sequential code receiving unit 1, as well as the counting triggers 7-9, the switching triggers 10 and 11 and the memory registers 3 and 4 are set to zero (the reset circuit is zero Fig. 1 is not shown)., Information from data transmission equipment (FDA) is received to the sequential code receiving unit 1 from input 28 accompanied by clock pulses, respectively received 66 but to inputs 26 and 27 shifted from one another relative to each other by half a period. When the information pulse arrives (input 28 j and tracking clock pulse (input 27), the output signal is element-NOT 39 sets the trigger 36 to one state and a single signal is fed to the information input of the shift register 38. At the same time, a pulse arrives at input 27 of the shift register 38 (since trigger 35 is in the zero state) and the information is recorded in it. The trigger Zb is set to the zero state by the clock pulse from input 2b. After a certain bit of information code arrives, the corresponding code is set at the output of the counter 33, and when the next clock pulse arrives at input 26, the signal from the output of the decoder 3 converts the trigger 35 into a single state, as a result of which the clock pulses from input 27 are forbidden to go to register recording 38 shear. This concludes the process of recording information in the shift register 38 and, from its output, information in a parallel code (output 31 of the serial code receiving unit 1) is fed to the input of the converter 2 codes. Then, input 29 from the ADF receives a signal confirming the arrival of information, followed by a clock pulse on bus 2J. and the signal from the output of the NAND 0 element (output 32 of the sequential code reception unit 1) is fed to the input of the trigger 7 and the NAND elements 17 and 18. At the output of the NAND 17 element, a signal appears that permits the recording of information from the register 38 the shift converted by the converter 2 of the code into a view that depends on the type of indicator used is recorded in the memory recorder 3 and the indicator 5 displays the symbol corresponding to the information received from the ADF. The signal from the output of the element AND-NOT 17 also sets the trigger 10 to one state and the pulses from the low-frequency generator 12 through the element AND-NE 21 arrive at the indicator 5 and the symbol displayed on it flashes at a frequency of 2 Hz, thereby attracting the attention of the operator to the received information.

The signal from the output of the NANDO element 0 also sets the trigger 37 to one state, as a result of which the signal from the output of the element OR 2 sets the counter 33 and the trigger 35 to the zero state, thereby preparing the device to receive the following information from the ADF, at the same time the same signal prohibits the passage of a clock pulse from input 27 through the element AND-NOT 4 to the input of the record of the shift register 38. The trigger 37 is brought to the zero state by the clock signals from the bus 26.

Upon receipt of the following information from the ADF, it is written in the shift register 38 in the same way as described above, and after receiving a confirmation signal on receipt of information on the bus 29, the signal from the output of the AND-NOT element 18 is recorded in the memory register and displayed on the indicator 6 in blinking mode, since the trigger 11 is set to one at the signal from the output of the element AND-NE 18 and pulses from the output of the generator 12 through the element AND-NOT 22 arrive at the indicator 6.

Upon receipt of subsequent marks of information, they are displayed on indicators 5 and 6 in order of arrival with the destruction of previously received information and the blinking of new information. In the controlled display mode, the incoming information is recorded in the shift register 38 in the same way as described. The order of the display of information on the indicators 5 and 6 is controlled by pressing the 2k and

25

When the button 24 is pressed for the first time, a signal arrives at the input of the trigger 8 with a counting input, and a pulse is generated at the output of the NE-HE element 19, which sets the trigger 10 to the zero state. At the same time, the flickering of the symbol on the indicator 5 stops and this symbol is permanently displayed. The second pressing of the button 24 at the output of the element 15 produces a signal that sets the memory register 3 to the zero state, and as a result the symbol on the indicator 5 goes out.

When the button 25 is pressed for the first time, a signal arrives at the input of the trigger 9, and a pulse is generated at the output of the AND-HE element 20, setting the trigger 11 to the zero state. At the same time, the flickering of the symbol on the indicator 6 stops and this symbol is permanently displayed. The second pressing of the button 25 at the output of the element AND 16 forms a signal that sets the memory register 4 to the zero state, and as a result

the symbol on the indicator 6.

Depending on the manipulations with buttons 24 and 25, the information received from the ADF is displayed as follows.

If the blinking of information on the indicator 6 is stopped {the button 25 is pressed), and the information on the indicator 5 is blinking, then the signal from the output of the AND-OR 13 element goes to the 5th input

trigger 7, set it to one. Therefore, when new information arrives, it will be recorded in memory register 4 by a signal from the output of the NAND 18 element and displayed on the indicator 6 in flickering mode 1 as the trigger 11 is set again (G unit state).

If the blinking of information on the indicator 5 is stopped (the button

24), and the information on the indicator 6 flashes, then the signal from the output of the AND-OR 14 element through the OR element 23 arrives at the R input of the trigger 7, setting it to the zero state. When new information arrives, it is recorded in memory register 3 and displayed on indicator 5 in flickering mode (since trigger 10 is set to the single state).

If the blinking of information on the indicator 5 1 is stopped, the button 24 is pressed) and then the information on the indicator 6 is destroyed (the button 25 is pressed twice), the signal from the output of the AND 16 element through the AND-OR element

13 (since the trigger 8 with the counting input is in the single state) sets the trigger 7 to the single state. The newly received information is displayed on the indicator 6 in flickering mode.

If the blinking of information on indicator 6 (button 25 is pressed) is stopped, and then the information on indicator 5 is destroyed (button 24 is pressed twice), the signal from the output of the AND 15 element through the AND-OR element

Claims (1)

14 (since the trigger 9 is in the 9 1 unit state) sets the trigger 7 to the zero state. Newly received information will be displayed on the indicator 5 in the flickering mode. The use of the proposed device allows increasing the reliability of communicating information to the operator. This is achieved by the fact that in the proposed device you provide flickering of the received information, as a result of which the operator's attention is drawn to the new information for its analysis and decision making. This is especially important when each successor designates some kind of command to one operator. In addition, it is possible for the operator to promptly intervene in the process of displaying information and managing the order in which information is displayed on the display panel of the device. In the mode of controlled display, the operator, having fulfilled the received command with the help of control buttons, can either leave the flickering of the displayed symbol, or erase it, leaving on the table information that has not yet been worked out, and the new information will be displayed in place. The invention includes a device for receiving and displaying information that contains a block for receiving a serial code, the first and second inputs of which are connected to the clock inputs of the device, the third and fourth inputs to the information inputs of the device, the fifth input to the input of the device to zero, the first the output of the sequential code reception unit is connected via a code converter to the first inputs of the first and second memory registers, the outputs of which are connected to the first inputs of the first and second indicators, respectively, distinguishing If, in order to increase the reliability of the received information, counting triggers, switching triggers, low-frequency generator, control buttons, AND, AND-OR, AND-NOT elements and the OR element, whose first input is connected to the device setup input, are entered into the device, the output of the OR element is connected to the zero input of the first 610. the counting trigger, the direct and inverse outputs of which are connected to the first inputs of the first and second IS-NOT, respectively, the second inputs of which are combined with the counting input of the first counting trigger and connected to the second output of the serial code receiving unit n with the second input of the first memory register, the single input of the first switching trigger and the zero input of the second counting trigger, the single output of which is connected to the first inputs of the first AND-OR element and the first element a AND, the second input of the first element AND, the first inputs of the third element NAND, the second element AND-OR, and the counting input of the second counting three are connected and connected to the first control button, the zero output of the second counting trigger is connected to the second input of the third AND- element NOT whose output is connected to the zero input of the first switching trigger, the output of the first switching trigger is connected to the first input of the fourth AND-NOT element and the second input of the first AND-OR element, the output of which is connected to the single input of the first counting t igger, the output of the first element AND is connected to the third input of the first memory register and the second input of the second AND-OR element, the output of which is connected to the second input of the OR element, the output of the second AND-NOT element is connected to the second input of the second memory register, the single input of the second the trigger trigger and the zero input of the third counting trigger, the single output of which is connected to the third input of the second AND-OR element and the first input of the second element AND whose output is connected to the third inputs of the second memory register and the first element nta AND-OR, the zero output of the third counting trigger is connected to the first input of the fifth NAND element, the second input of which, the second input of the second element AND, the fourth input of the first element AND-OR, and the counting input of the third counting switching trigger are connected and connected to to the second control button, the output of the N element of the NAND is connected to the zero input of the second switching trigger, the output of which is connected to the fourth input of the second element IL-n and n1003-L the first input of the sixth element NAND, the second inputs of the fourth and neck 11 combined and connected to the output of the low-frequency generator, the outputs of the fourth and sixth elements of the NAND are connected to the second inputs of the first and second indicators, respectively. 126 12 Sources of information taken into account during the examination 1. USSR author's certificate 5 No. 524216, cl, G 08 C 19/28, 1975. 2, USSR author's certificate No. 907569, cl. G 08 C 19/28, 1980 (prototype).