SG87934A1 - A method of fabricating cmos devices featuring dual gate structures and a high dielectric constant gate insulator layer - Google Patents

A method of fabricating cmos devices featuring dual gate structures and a high dielectric constant gate insulator layer

Info

Publication number
SG87934A1
SG87934A1 SG200103338A SG200103338A SG87934A1 SG 87934 A1 SG87934 A1 SG 87934A1 SG 200103338 A SG200103338 A SG 200103338A SG 200103338 A SG200103338 A SG 200103338A SG 87934 A1 SG87934 A1 SG 87934A1
Authority
SG
Singapore
Prior art keywords
dielectric constant
insulator layer
high dielectric
cmos devices
devices featuring
Prior art date
Application number
SG200103338A
Inventor
Liang Cha Randall Cher
See Alex
Chan Lap
Original Assignee
Chartered Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chartered Semiconductor Mfg filed Critical Chartered Semiconductor Mfg
Publication of SG87934A1 publication Critical patent/SG87934A1/en

Links

SG200103338A 2000-06-30 2001-06-05 A method of fabricating cmos devices featuring dual gate structures and a high dielectric constant gate insulator layer SG87934A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US72820000P 2000-06-30 2000-06-30

Publications (1)

Publication Number Publication Date
SG87934A1 true SG87934A1 (en) 2002-04-16

Family

ID=24925824

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200103338A SG87934A1 (en) 2000-06-30 2001-06-05 A method of fabricating cmos devices featuring dual gate structures and a high dielectric constant gate insulator layer

Country Status (1)

Country Link
SG (1) SG87934A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5112765A (en) * 1990-07-31 1992-05-12 International Business Machines Corporation Method of forming stacked tungsten gate PFET devices and structures resulting therefrom
US5480830A (en) * 1995-04-04 1996-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Method of making depleted gate transistor for high voltage operation
US5731239A (en) * 1997-01-22 1998-03-24 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5112765A (en) * 1990-07-31 1992-05-12 International Business Machines Corporation Method of forming stacked tungsten gate PFET devices and structures resulting therefrom
US5480830A (en) * 1995-04-04 1996-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Method of making depleted gate transistor for high voltage operation
US5731239A (en) * 1997-01-22 1998-03-24 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance

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