SG44604A1 - Circuit and method of interconnecting content addressable memory - Google Patents
Circuit and method of interconnecting content addressable memoryInfo
- Publication number
- SG44604A1 SG44604A1 SG1996003572A SG1996003572A SG44604A1 SG 44604 A1 SG44604 A1 SG 44604A1 SG 1996003572 A SG1996003572 A SG 1996003572A SG 1996003572 A SG1996003572 A SG 1996003572A SG 44604 A1 SG44604 A1 SG 44604A1
- Authority
- SG
- Singapore
- Prior art keywords
- circuit
- addressable memory
- content addressable
- interconnecting
- interconnecting content
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12355193A | 1993-09-20 | 1993-09-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG44604A1 true SG44604A1 (en) | 1997-12-19 |
Family
ID=22409334
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG1996003572A SG44604A1 (en) | 1993-09-20 | 1994-09-15 | Circuit and method of interconnecting content addressable memory |
Country Status (4)
Country | Link |
---|---|
US (1) | US5467319A (fr) |
EP (1) | EP0644553B1 (fr) |
DE (1) | DE69425209T2 (fr) |
SG (1) | SG44604A1 (fr) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5712820A (en) * | 1995-11-17 | 1998-01-27 | Cypress Semiconductor Corporation | Multiple word width memory array clocking scheme |
US5642318A (en) * | 1995-12-05 | 1997-06-24 | Cypress Semicondcutor Corporation | Testing method for FIFOS |
US5809339A (en) * | 1995-12-06 | 1998-09-15 | Cypress Semiconductor Corp. | State machine design for generating half-full and half-empty flags in an asynchronous FIFO |
US5712992A (en) * | 1995-12-06 | 1998-01-27 | Cypress Semiconductor Corporation | State machine design for generating empty and full flags in an asynchronous FIFO |
US5673234A (en) * | 1995-12-13 | 1997-09-30 | Cypress Semiconductor Corp. | Read bitline writer for fallthru in FIFO's |
US5963056A (en) * | 1995-12-14 | 1999-10-05 | Cypress Semiconductor Corp. | Full and empty flag generator for synchronous FIFOs |
US5844423A (en) * | 1995-12-14 | 1998-12-01 | Cypress Semiconductor Corporation | Half-full flag generator for synchronous FIFOs |
US5880997A (en) * | 1995-12-22 | 1999-03-09 | Cypress Semiconductor Corp. | Bubbleback for FIFOS |
US5850568A (en) * | 1995-12-22 | 1998-12-15 | Cypress Semiconductor Corporation | Circuit having plurality of carry/sum adders having read count, write count, and offset inputs to generate an output flag in response to FIFO fullness |
US5852748A (en) * | 1995-12-29 | 1998-12-22 | Cypress Semiconductor Corp. | Programmable read-write word line equality signal generation for FIFOs |
US5682356A (en) * | 1996-01-11 | 1997-10-28 | Cypress Semiconductor Corp. | Multiple word width memory array clocking scheme for reading words from a memory array |
US5661418A (en) * | 1996-03-13 | 1997-08-26 | Cypress Semiconductor Corp. | Signal generation decoder circuit and method |
US6510486B1 (en) | 1996-03-25 | 2003-01-21 | Cypress Semiconductor Corp. | Clocking scheme for independently reading and writing multiple width words from a memory array |
US5764967A (en) * | 1996-03-29 | 1998-06-09 | Cypress Semiconductor Corporation | Multiple frequency memory array clocking scheme for reading and writing multiple width digital words |
US5872802A (en) * | 1996-05-03 | 1999-02-16 | Cypress Semiconductor Corp. | Parity generation and check circuit and method in read data path |
US5812465A (en) * | 1996-08-02 | 1998-09-22 | Cypress Semiconductor Corp. | Redundancy circuit and method for providing word lines driven by a shift register |
US6023777A (en) * | 1996-09-11 | 2000-02-08 | Cypress Semiconductor Corp. | Testing method for devices with status flags |
US5968190A (en) * | 1996-10-31 | 1999-10-19 | Cypress Semiconductor Corp. | Redundancy method and circuit for self-repairing memory arrays |
US5860160A (en) * | 1996-12-18 | 1999-01-12 | Cypress Semiconductor Corp. | High speed FIFO mark and retransmit scheme using latches and precharge |
US5964857A (en) * | 1997-05-30 | 1999-10-12 | Quality Semiconductor, Inc. | Priority encoder for a content addressable memory system |
US5930790A (en) * | 1997-09-25 | 1999-07-27 | Xerox Corporation | String-match array for substitutional compression |
US6892272B1 (en) | 1999-02-23 | 2005-05-10 | Netlogic Microsystems, Inc. | Method and apparatus for determining a longest prefix match in a content addressable memory device |
JP3813758B2 (ja) * | 1999-04-12 | 2006-08-23 | エルピーダメモリ株式会社 | 半導体記憶装置 |
US6191969B1 (en) * | 1999-09-09 | 2001-02-20 | Net Logic Microsystems, Inc. | Selective match line discharging in a partitioned content addressable memory array |
US6392910B1 (en) * | 1999-09-10 | 2002-05-21 | Sibercore Technologies, Inc. | Priority encoder with multiple match function for content addressable memories and methods for implementing the same |
US6934795B2 (en) | 1999-09-23 | 2005-08-23 | Netlogic Microsystems, Inc. | Content addressable memory with programmable word width and programmable priority |
US6567340B1 (en) * | 1999-09-23 | 2003-05-20 | Netlogic Microsystems, Inc. | Memory storage cell based array of counters |
US7272027B2 (en) | 1999-09-23 | 2007-09-18 | Netlogic Microsystems, Inc. | Priority circuit for content addressable memory |
US6944709B2 (en) | 1999-09-23 | 2005-09-13 | Netlogic Microsystems, Inc. | Content addressable memory with block-programmable mask write mode, word width and priority |
US7143231B1 (en) | 1999-09-23 | 2006-11-28 | Netlogic Microsystems, Inc. | Method and apparatus for performing packet classification for policy-based packet routing |
US7669005B1 (en) | 2001-06-18 | 2010-02-23 | Netlogic Microsystems, Inc. | Content addressable memory (CAM) devices having soft priority resolution circuits therein and methods of operating same |
US6996662B2 (en) * | 2001-06-18 | 2006-02-07 | Integrated Device Technology, Inc. | Content addressable memory array having flexible priority support |
US7301961B1 (en) | 2001-12-27 | 2007-11-27 | Cypress Semiconductor Corportion | Method and apparatus for configuring signal lines according to idle codes |
US20130027416A1 (en) * | 2011-07-25 | 2013-01-31 | Karthikeyan Vaithianathan | Gather method and apparatus for media processing accelerators |
US20130170273A1 (en) * | 2011-12-29 | 2013-07-04 | Lsi Corporation | Content-Addressable Memory Architecture for Routing Raw Hit Lines Using Minimal Base Metal Layers |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1240063A (fr) * | 1986-02-25 | 1988-08-02 | Milan Skubnik | Circuit de compression-expansion numerique |
US4928260A (en) * | 1988-05-11 | 1990-05-22 | Advanced Micro Devices, Inc. | Content addressable memory array with priority encoder |
US5003307A (en) * | 1989-01-13 | 1991-03-26 | Stac, Inc. | Data compression apparatus with shift register search means |
AU624205B2 (en) * | 1989-01-23 | 1992-06-04 | General Electric Capital Corporation | Variable length string matcher |
US5060242A (en) * | 1989-02-24 | 1991-10-22 | General Electric Company | Non-destructive lossless image coder |
JP2922571B2 (ja) * | 1990-04-05 | 1999-07-26 | キヤノン株式会社 | データ変換回路 |
US5317708A (en) * | 1990-06-29 | 1994-05-31 | Digital Equipment Corporation | Apparatus and method for an improved content addressable memory |
US5319762A (en) * | 1990-09-07 | 1994-06-07 | The Mitre Corporation | Associative memory capable of matching a variable indicator in one string of characters with a portion of another string |
US5151697A (en) * | 1990-10-15 | 1992-09-29 | Board Of Regents Of The University Of Washington | Data structure management tagging system |
-
1994
- 1994-09-15 DE DE69425209T patent/DE69425209T2/de not_active Expired - Fee Related
- 1994-09-15 EP EP94114546A patent/EP0644553B1/fr not_active Expired - Lifetime
- 1994-09-15 SG SG1996003572A patent/SG44604A1/en unknown
-
1995
- 1995-04-07 US US08/418,908 patent/US5467319A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69425209T2 (de) | 2001-03-15 |
EP0644553A3 (fr) | 1995-09-06 |
DE69425209D1 (de) | 2000-08-17 |
US5467319A (en) | 1995-11-14 |
EP0644553B1 (fr) | 2000-07-12 |
EP0644553A2 (fr) | 1995-03-22 |
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