SG170615A1 - Stacked die in die bga package - Google Patents

Stacked die in die bga package

Info

Publication number
SG170615A1
SG170615A1 SG200700710-7A SG2007007107A SG170615A1 SG 170615 A1 SG170615 A1 SG 170615A1 SG 2007007107 A SG2007007107 A SG 2007007107A SG 170615 A1 SG170615 A1 SG 170615A1
Authority
SG
Singapore
Prior art keywords
die
stacked
bga package
substrate
clearance
Prior art date
Application number
SG200700710-7A
Inventor
Hock Chuan Tan
Thiam Chye Lim
Victor Cher Khng Tan
Chee Peng Neo
Michael Kian Shing Tan
Beng Chye Chew
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to SG200700710-7A priority Critical patent/SG170615A1/en
Publication of SG170615A1 publication Critical patent/SG170615A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Wire Bonding (AREA)

Abstract

A stacked die assembly is disclosed which eliminates the need for the spacer between stacked dies that allowing clearance for the bonding leads/wires to the substrate. A first die 42 is positioned on a substrate 44 with a second die 46 positioned on top. The underside perimeter of the second die is recessed 63 to allow a clearance for the bonding wires 50a. Figure No. 4
SG200700710-7A 2002-01-09 2002-01-09 Stacked die in die bga package SG170615A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SG200700710-7A SG170615A1 (en) 2002-01-09 2002-01-09 Stacked die in die bga package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG200700710-7A SG170615A1 (en) 2002-01-09 2002-01-09 Stacked die in die bga package

Publications (1)

Publication Number Publication Date
SG170615A1 true SG170615A1 (en) 2011-05-30

Family

ID=44359599

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200700710-7A SG170615A1 (en) 2002-01-09 2002-01-09 Stacked die in die bga package

Country Status (1)

Country Link
SG (1) SG170615A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5019943A (en) * 1990-02-14 1991-05-28 Unisys Corporation High density chip stack having a zigzag-shaped face which accommodates connections between chips
US5804004A (en) * 1992-05-11 1998-09-08 Nchip, Inc. Stacked devices for multichip modules
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5019943A (en) * 1990-02-14 1991-05-28 Unisys Corporation High density chip stack having a zigzag-shaped face which accommodates connections between chips
US5804004A (en) * 1992-05-11 1998-09-08 Nchip, Inc. Stacked devices for multichip modules
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers

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