SG148594G - Data processing system and method with management of a mass storage buffer - Google Patents
Data processing system and method with management of a mass storage bufferInfo
- Publication number
- SG148594G SG148594G SG148594A SG148594A SG148594G SG 148594 G SG148594 G SG 148594G SG 148594 A SG148594 A SG 148594A SG 148594 A SG148594 A SG 148594A SG 148594 G SG148594 G SG 148594G
- Authority
- SG
- Singapore
- Prior art keywords
- management
- data processing
- processing system
- mass storage
- storage buffer
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62319128A JPH0650479B2 (ja) | 1987-02-13 | 1987-12-18 | データ処理装置 |
DE3889678T DE3889678T2 (de) | 1987-02-13 | 1988-02-05 | Datenverarbeitungsanordnung und Verfahren mit Massenspeicherpufferverwaltung. |
EP88101695A EP0278425B1 (fr) | 1987-02-13 | 1988-02-05 | Système et procédé de traitement de données avec gestion d'un tampon de mémoire de masse |
US07/735,110 US5136692A (en) | 1987-02-13 | 1991-07-24 | Memory disk buffer manager |
SG148594A SG148594G (en) | 1987-02-13 | 1994-10-13 | Data processing system and method with management of a mass storage buffer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US1490187A | 1987-02-13 | 1987-02-13 | |
SG148594A SG148594G (en) | 1987-02-13 | 1994-10-13 | Data processing system and method with management of a mass storage buffer |
Publications (1)
Publication Number | Publication Date |
---|---|
SG148594G true SG148594G (en) | 1995-03-17 |
Family
ID=26664423
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG148594A SG148594G (en) | 1987-02-13 | 1994-10-13 | Data processing system and method with management of a mass storage buffer |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0278425B1 (fr) |
JP (1) | JPH0650479B2 (fr) |
DE (1) | DE3889678T2 (fr) |
SG (1) | SG148594G (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB9019891D0 (en) * | 1990-09-12 | 1990-10-24 | Di Data Ltd | Computer memory array control |
US5640596A (en) * | 1992-03-10 | 1997-06-17 | Hitachi, Ltd. | Input output control system for transferring control programs collectively as one transfer unit designated by plurality of input output requests to be executed |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4437155A (en) * | 1980-11-14 | 1984-03-13 | Sperry Corporation | Cache/disk subsystem with dual aging of cache entries |
JPS57172457A (en) * | 1981-04-17 | 1982-10-23 | Hitachi Ltd | Secondary storage controller |
US4536836A (en) * | 1981-11-27 | 1985-08-20 | Storage Technology Corporation | Detection of sequential data stream |
US4530055A (en) * | 1982-03-03 | 1985-07-16 | Sperry Corporation | Hierarchical memory system with variable regulation and priority of writeback from cache memory to bulk memory |
JPS60230247A (ja) * | 1984-04-27 | 1985-11-15 | Panafacom Ltd | デイスク制御装置 |
JPS61235957A (ja) * | 1985-04-11 | 1986-10-21 | Nec Corp | デ−タ制御方式 |
-
1987
- 1987-12-18 JP JP62319128A patent/JPH0650479B2/ja not_active Expired - Fee Related
-
1988
- 1988-02-05 DE DE3889678T patent/DE3889678T2/de not_active Expired - Fee Related
- 1988-02-05 EP EP88101695A patent/EP0278425B1/fr not_active Expired - Lifetime
-
1994
- 1994-10-13 SG SG148594A patent/SG148594G/en unknown
Also Published As
Publication number | Publication date |
---|---|
DE3889678T2 (de) | 1994-12-01 |
EP0278425B1 (fr) | 1994-05-25 |
DE3889678D1 (de) | 1994-06-30 |
JPH0650479B2 (ja) | 1994-06-29 |
EP0278425A3 (en) | 1990-08-01 |
EP0278425A2 (fr) | 1988-08-17 |
JPS63204448A (ja) | 1988-08-24 |
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