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Priority claimed from US12/124,880external-prioritypatent/US7883938B2/en
Application filed by United Test & Assembly Ct LtfiledCriticalUnited Test & Assembly Ct Lt
Publication of SG148132A1publicationCriticalpatent/SG148132A1/en
METHOD OF ASSEMBLING A STACKED DIE SEMICONDUCTOR PACKAGE A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a plurality of open vias, and the open vias of the second and third silicon wafers are aligned with one another; etching a bonding material that attaches the wafers from the aligned open vias; filling the aligned open vias with a conductor; forming conductive bumps at open ends of the aligned open vias; back grinding the first silicon wafer; separating the stacked semiconductor dies from each other; attaching the bump end of the stacked semiconductor dies onto a substrate; encapsulating the stacked semiconductor dies and substrate; and singulating the encapsulated assembly.
SG200803945-5A2007-05-222008-05-22Method of assembling a stacked die semiconductor package
SG148132A1
(en)
Semiconductor device and method of forming tsv interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
Semiconductor device and method of forming bond wires between semiconductor die contact pads and conductive TOV in peripheral area around semiconductor die