SG142201A1 - Method for fabricating a dual damascene structure - Google Patents

Method for fabricating a dual damascene structure

Info

Publication number
SG142201A1
SG142201A1 SG200607730-9A SG2006077309A SG142201A1 SG 142201 A1 SG142201 A1 SG 142201A1 SG 2006077309 A SG2006077309 A SG 2006077309A SG 142201 A1 SG142201 A1 SG 142201A1
Authority
SG
Singapore
Prior art keywords
layer
fabricating
dielectric layer
dual damascene
damascene structure
Prior art date
Application number
SG200607730-9A
Inventor
Hong Ma
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to SG200607730-9A priority Critical patent/SG142201A1/en
Publication of SG142201A1 publication Critical patent/SG142201A1/en

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

METHOD FOR FABRICATING A DUAL DAMASCENE STRUCTURE A method for fabricating a dual damascene structure contains providing a substrate having a conductive layer, an etching stop layer, a dielectric layer, and a photoresist layer thereon, performing an etching process to remove a portion of the dielectric layer through a via pattern of the photoresist layer for forming a via structure in the dielectric layer, providing CO-containing gas to perform an ash process, filling GFP materials into the via structure, forming a photoresist layer with a trench pattern on the substrate, etching the dielectric layer through the trench pattern to form a trench structure in the dielectric layer, above the via structure, and removing the etching stop layer exposed in the via structure. Figure 15
SG200607730-9A 2006-11-07 2006-11-07 Method for fabricating a dual damascene structure SG142201A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SG200607730-9A SG142201A1 (en) 2006-11-07 2006-11-07 Method for fabricating a dual damascene structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG200607730-9A SG142201A1 (en) 2006-11-07 2006-11-07 Method for fabricating a dual damascene structure

Publications (1)

Publication Number Publication Date
SG142201A1 true SG142201A1 (en) 2008-05-28

Family

ID=39426740

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200607730-9A SG142201A1 (en) 2006-11-07 2006-11-07 Method for fabricating a dual damascene structure

Country Status (1)

Country Link
SG (1) SG142201A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6042996A (en) * 1998-02-13 2000-03-28 United Microelectronics Corp. Method of fabricating a dual damascene structure
US6093508A (en) * 1997-03-28 2000-07-25 International Business Machines Corporation Dual damascene structure formed in a single photoresist film
US6150269A (en) * 1998-09-11 2000-11-21 Chartered Semiconductor Manufacturing Company, Ltd. Copper interconnect patterning
US6649531B2 (en) * 2001-11-26 2003-11-18 International Business Machines Corporation Process for forming a damascene structure
US6872666B2 (en) * 2002-11-06 2005-03-29 Intel Corporation Method for making a dual damascene interconnect using a dual hard mask
US20060024971A1 (en) * 2004-07-30 2006-02-02 Samsung Electronics Co., Ltd. Dry etching method using polymer mask selectively formed by CO gas

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093508A (en) * 1997-03-28 2000-07-25 International Business Machines Corporation Dual damascene structure formed in a single photoresist film
US6042996A (en) * 1998-02-13 2000-03-28 United Microelectronics Corp. Method of fabricating a dual damascene structure
US6150269A (en) * 1998-09-11 2000-11-21 Chartered Semiconductor Manufacturing Company, Ltd. Copper interconnect patterning
US6649531B2 (en) * 2001-11-26 2003-11-18 International Business Machines Corporation Process for forming a damascene structure
US6872666B2 (en) * 2002-11-06 2005-03-29 Intel Corporation Method for making a dual damascene interconnect using a dual hard mask
US20060024971A1 (en) * 2004-07-30 2006-02-02 Samsung Electronics Co., Ltd. Dry etching method using polymer mask selectively formed by CO gas

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