SG130074A1 - Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices - Google Patents
Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devicesInfo
- Publication number
- SG130074A1 SG130074A1 SG200505618-9A SG2005056189A SG130074A1 SG 130074 A1 SG130074 A1 SG 130074A1 SG 2005056189 A SG2005056189 A SG 2005056189A SG 130074 A1 SG130074 A1 SG 130074A1
- Authority
- SG
- Singapore
- Prior art keywords
- methods
- substrates
- microelectronic
- forming
- packaging
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed herein. A method of manufacturing a substrate in accordance with one embodiment of the invention includes forming a conductive trace on a first side of a sheet of non-conductive material, and forming a via through the non-conductive material from a second side of the sheet to the conductive trace. The method further includes removing a section of the non-conductive material to form an edge of the non-conductive material extending across at least a portion of the via. In one embodiment, forming the edge across the via exposes at least a portion of the second conductive trace for subsequent attachment to a terminal on a microelectronic die.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG200505618-9A SG130074A1 (en) | 2005-09-01 | 2005-09-01 | Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG200505618-9A SG130074A1 (en) | 2005-09-01 | 2005-09-01 | Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices |
Publications (1)
Publication Number | Publication Date |
---|---|
SG130074A1 true SG130074A1 (en) | 2007-03-20 |
Family
ID=38787688
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200505618-9A SG130074A1 (en) | 2005-09-01 | 2005-09-01 | Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices |
Country Status (1)
Country | Link |
---|---|
SG (1) | SG130074A1 (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6214641B1 (en) * | 1996-06-25 | 2001-04-10 | Micron Technology, Inc. | Method of fabricating a multi-chip module |
US20030116866A1 (en) * | 2001-12-20 | 2003-06-26 | Cher 'khng Victor Tan | Semiconductor package having substrate with multi-layer metal bumps |
US20030150641A1 (en) * | 2002-02-14 | 2003-08-14 | Noyan Kinayman | Multilayer package for a semiconductor device |
US20030164303A1 (en) * | 2002-03-04 | 2003-09-04 | Fu-Yu Huang | Method of metal electro-plating for IC package substrate |
US20050112871A1 (en) * | 2000-05-31 | 2005-05-26 | Micron Technology, Inc. | Multilevel copper interconnect with double passivation |
-
2005
- 2005-09-01 SG SG200505618-9A patent/SG130074A1/en unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6214641B1 (en) * | 1996-06-25 | 2001-04-10 | Micron Technology, Inc. | Method of fabricating a multi-chip module |
US20050112871A1 (en) * | 2000-05-31 | 2005-05-26 | Micron Technology, Inc. | Multilevel copper interconnect with double passivation |
US20030116866A1 (en) * | 2001-12-20 | 2003-06-26 | Cher 'khng Victor Tan | Semiconductor package having substrate with multi-layer metal bumps |
US20030150641A1 (en) * | 2002-02-14 | 2003-08-14 | Noyan Kinayman | Multilayer package for a semiconductor device |
US20030164303A1 (en) * | 2002-03-04 | 2003-09-04 | Fu-Yu Huang | Method of metal electro-plating for IC package substrate |
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