SG11202110985PA - Assemblies which include wordlines having a first metal-containing material at least partially surrounding a second metal-containing material and having different crystallinity than the second metal-containing material - Google Patents

Assemblies which include wordlines having a first metal-containing material at least partially surrounding a second metal-containing material and having different crystallinity than the second metal-containing material

Info

Publication number
SG11202110985PA
SG11202110985PA SG11202110985PA SG11202110985PA SG11202110985PA SG 11202110985P A SG11202110985P A SG 11202110985PA SG 11202110985P A SG11202110985P A SG 11202110985PA SG 11202110985P A SG11202110985P A SG 11202110985PA SG 11202110985P A SG11202110985P A SG 11202110985PA
Authority
SG
Singapore
Prior art keywords
metal
containing material
assemblies
partially surrounding
different crystallinity
Prior art date
Application number
SG11202110985PA
Inventor
Jordan Greenlee
Rita Klein
Everett Mcteer
John Meldrim
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG11202110985PA publication Critical patent/SG11202110985PA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Composite Materials (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Electrodes Of Semiconductors (AREA)
SG11202110985PA 2019-04-15 2020-03-03 Assemblies which include wordlines having a first metal-containing material at least partially surrounding a second metal-containing material and having different crystallinity than the second metal-containing material SG11202110985PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/383,862 US11158718B2 (en) 2019-04-15 2019-04-15 Assemblies which include wordlines having a first metal-containing material at least partially surrounding a second metal-containing material and having different crystallinity than the second metal-containing material
PCT/US2020/020844 WO2020214268A1 (en) 2019-04-15 2020-03-03 Assemblies which include wordlines having a first metal-containing material at least partially surrounding a second metal-containing material and having different crystallinity than the second metal-containing material

Publications (1)

Publication Number Publication Date
SG11202110985PA true SG11202110985PA (en) 2021-10-28

Family

ID=72748229

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202110985PA SG11202110985PA (en) 2019-04-15 2020-03-03 Assemblies which include wordlines having a first metal-containing material at least partially surrounding a second metal-containing material and having different crystallinity than the second metal-containing material

Country Status (8)

Country Link
US (2) US11158718B2 (en)
EP (1) EP3956927A4 (en)
JP (1) JP2022529426A (en)
KR (1) KR20210138796A (en)
CN (1) CN113711355A (en)
SG (1) SG11202110985PA (en)
TW (1) TW202042236A (en)
WO (1) WO2020214268A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10957775B2 (en) 2019-07-01 2021-03-23 Micron Technology, Inc. Assemblies having conductive structures with three or more different materials
KR20220154284A (en) * 2021-05-12 2022-11-22 삼성전자주식회사 Semiconductor memory device and method of fabricating the same
TW202318576A (en) * 2021-08-03 2023-05-01 美商應用材料股份有限公司 Selective silicide deposition for 3-d dram
US11990413B2 (en) * 2021-08-11 2024-05-21 Sandisk Technologies Llc Three-dimensional memory device including aluminum alloy word lines and method of making the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009182114A (en) * 2008-01-30 2009-08-13 Elpida Memory Inc Semiconductor device and manufacturing method thereof
US8258034B2 (en) 2009-08-26 2012-09-04 Micron Technology, Inc. Charge-trap based memory
US8592873B2 (en) 2010-06-24 2013-11-26 Samsung Electronics Co., Ltd. Semiconductor memory devices and methods of forming the same
KR20120118947A (en) 2011-04-20 2012-10-30 삼성전자주식회사 Vertical memory devices and methods of manufacturing the same
BR112016002576A2 (en) * 2013-08-13 2017-08-01 Propocean As stabilization of a rising column tube
JP6360457B2 (en) * 2015-04-08 2018-07-18 東芝メモリ株式会社 Semiconductor device and manufacturing method thereof
KR102447489B1 (en) 2015-09-02 2022-09-27 삼성전자주식회사 Semiconductor memory device
US9793139B2 (en) 2015-10-29 2017-10-17 Sandisk Technologies Llc Robust nucleation layers for enhanced fluorine protection and stress reduction in 3D NAND word lines
JP6581019B2 (en) * 2016-03-02 2019-09-25 東芝メモリ株式会社 Semiconductor memory device
US10361213B2 (en) 2016-06-28 2019-07-23 Sandisk Technologies Llc Three dimensional memory device containing multilayer wordline barrier films and method of making thereof
US10453798B2 (en) * 2017-09-27 2019-10-22 Sandisk Technologies Llc Three-dimensional memory device with gated contact via structures and method of making thereof

Also Published As

Publication number Publication date
TW202042236A (en) 2020-11-16
CN113711355A (en) 2021-11-26
US20220028996A1 (en) 2022-01-27
EP3956927A1 (en) 2022-02-23
US20200328284A1 (en) 2020-10-15
JP2022529426A (en) 2022-06-22
KR20210138796A (en) 2021-11-19
EP3956927A4 (en) 2023-01-18
WO2020214268A1 (en) 2020-10-22
US11158718B2 (en) 2021-10-26

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