SG11202011788YA - Substrate for an integrated radiofrequency device and method for manufacturing same - Google Patents

Substrate for an integrated radiofrequency device and method for manufacturing same

Info

Publication number
SG11202011788YA
SG11202011788YA SG11202011788YA SG11202011788YA SG11202011788YA SG 11202011788Y A SG11202011788Y A SG 11202011788YA SG 11202011788Y A SG11202011788Y A SG 11202011788YA SG 11202011788Y A SG11202011788Y A SG 11202011788YA SG 11202011788Y A SG11202011788Y A SG 11202011788YA
Authority
SG
Singapore
Prior art keywords
substrate
manufacturing same
radiofrequency device
integrated radiofrequency
integrated
Prior art date
Application number
SG11202011788YA
Inventor
Christelle Veytizou
Patrick Reynaud
Oleg Kononchuk
Frédéric Allibert
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202011788YA publication Critical patent/SG11202011788YA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/12Supports; Mounting means
    • H01Q1/22Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Recrystallisation Techniques (AREA)
SG11202011788YA 2018-07-05 2018-07-05 Substrate for an integrated radiofrequency device and method for manufacturing same SG11202011788YA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/FR2018/051683 WO2020008116A1 (en) 2018-07-05 2018-07-05 Substrate for an integrated radiofrequency device, and process for manufacturing same

Publications (1)

Publication Number Publication Date
SG11202011788YA true SG11202011788YA (en) 2020-12-30

Family

ID=63449488

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202011788YA SG11202011788YA (en) 2018-07-05 2018-07-05 Substrate for an integrated radiofrequency device and method for manufacturing same

Country Status (7)

Country Link
US (1) US20210183691A1 (en)
EP (1) EP3818561A1 (en)
JP (1) JP7230297B2 (en)
KR (1) KR102652250B1 (en)
CN (1) CN112236853B (en)
SG (1) SG11202011788YA (en)
WO (1) WO2020008116A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3121548B1 (en) 2021-03-30 2024-02-16 Soitec Silicon On Insulator METHOD FOR PREPARING AN ADVANCED SUBSTRATE, PARTICULARLY FOR PHOTONIC APPLICATIONS
FR3113184B1 (en) 2020-07-28 2022-09-16 Soitec Silicon On Insulator METHOD FOR PREPARING A SUPPORT SUBSTRATE, AND METHOD FOR TRANSFERRING A THIN LAYER ONTO THIS SUPPORT SUBSTRATE
WO2022023630A1 (en) 2020-07-28 2022-02-03 Soitec Method for transferring a thin layer onto a support substrate provided with a charge trapping layer
FR3129028B1 (en) 2021-11-09 2023-11-10 Soitec Silicon On Insulator METHOD FOR PREPARING A SUPPORT SUBSTRATE PROVIDED WITH A CHARGE TRAPPING LAYER
FR3129029B1 (en) 2021-11-09 2023-09-29 Soitec Silicon On Insulator METHOD FOR PREPARING A SUPPORT SUBSTRATE PROVIDED WITH A CHARGE TRAPPING LAYER

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1221805A (en) * 1997-11-05 1999-07-07 国际商业机器公司 Method for forming noble metal oxides and structures formed thereof
JP3690565B2 (en) * 1998-06-26 2005-08-31 富士通株式会社 Laminated structure, wiring structure, manufacturing method thereof, and semiconductor device
EP1087041B1 (en) 1999-03-16 2009-01-07 Shin-Etsu Handotai Co., Ltd Production method for silicon wafer and silicon wafer
WO2002082514A1 (en) * 2001-04-04 2002-10-17 Massachusetts Institute Of Technology A method for semiconductor device fabrication
FR2838865B1 (en) 2002-04-23 2005-10-14 Soitec Silicon On Insulator PROCESS FOR PRODUCING A SUBSTRATE WITH USEFUL LAYER ON HIGH RESISTIVITY SUPPORT
FR2860341B1 (en) 2003-09-26 2005-12-30 Soitec Silicon On Insulator METHOD FOR MANUFACTURING LOWERED LOWER MULTILAYER STRUCTURE
FR2868204B1 (en) * 2004-03-25 2006-06-16 Commissariat Energie Atomique SEMICONDUCTOR-TYPE SUBSTRATE ON INSULATION COMPRISING A CARBON DIAMOND BURIED LAYER
US7732301B1 (en) * 2007-04-20 2010-06-08 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
FR2933233B1 (en) 2008-06-30 2010-11-26 Soitec Silicon On Insulator GOOD RESISTANCE HIGH RESISTIVITY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
KR20110093780A (en) * 2008-11-12 2011-08-18 도요 고한 가부시키가이샤 Polymer laminate substrate for formation of epitaxially grown film, and manufacturing method therefor
JP2010258083A (en) * 2009-04-22 2010-11-11 Panasonic Corp Soi wafer, method for producing the same, and method for manufacturing semiconductor device
FR2953640B1 (en) 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech METHOD FOR MANUFACTURING A SEMICONDUCTOR TYPE STRUCTURE ON INSULATION, WITH REDUCED ELECTRICAL LOSSES AND CORRESPONDING STRUCTURE
FR2973158B1 (en) * 2011-03-22 2014-02-28 Soitec Silicon On Insulator METHOD FOR MANUFACTURING SEMICONDUCTOR-TYPE SUBSTRATE ON INSULATION FOR RADIO FREQUENCY APPLICATIONS
US8741739B2 (en) 2012-01-03 2014-06-03 International Business Machines Corporation High resistivity silicon-on-insulator substrate and method of forming
US8680511B2 (en) * 2012-02-09 2014-03-25 International Business Machines Corporation Bilayer gate dielectric with low equivalent oxide thickness for graphene devices
US9768056B2 (en) 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
US10079170B2 (en) * 2014-01-23 2018-09-18 Globalwafers Co., Ltd. High resistivity SOI wafers and a method of manufacturing thereof
FR3024587B1 (en) * 2014-08-01 2018-01-26 Soitec METHOD FOR MANUFACTURING HIGHLY RESISTIVE STRUCTURE
US9853133B2 (en) 2014-09-04 2017-12-26 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity silicon-on-insulator substrate
US10312134B2 (en) * 2014-09-04 2019-06-04 Globalwafers Co., Ltd. High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
FR3029682B1 (en) * 2014-12-04 2017-12-29 Soitec Silicon On Insulator HIGH RESISTIVITY SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
CN107533953B (en) * 2015-03-03 2021-05-11 环球晶圆股份有限公司 Method for depositing a charge trapping polysilicon film on a silicon substrate with controlled film stress
EP3144958B1 (en) * 2015-09-17 2021-03-17 Soitec Structure for radiofrequency applications and process for manufacturing such a structure
FR3048306B1 (en) * 2016-02-26 2018-03-16 Soitec SUPPORT FOR A SEMICONDUCTOR STRUCTURE
JP6848846B2 (en) * 2017-12-19 2021-03-24 株式会社Sumco Manufacturing method of bonded wafer and bonded wafer

Also Published As

Publication number Publication date
JP7230297B2 (en) 2023-03-01
US20210183691A1 (en) 2021-06-17
KR20210027261A (en) 2021-03-10
JP2021532567A (en) 2021-11-25
CN112236853A (en) 2021-01-15
EP3818561A1 (en) 2021-05-12
WO2020008116A1 (en) 2020-01-09
KR102652250B1 (en) 2024-03-28
CN112236853B (en) 2024-09-13

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