FR3129028B1 - METHOD FOR PREPARING A SUPPORT SUBSTRATE PROVIDED WITH A CHARGE TRAPPING LAYER - Google Patents

METHOD FOR PREPARING A SUPPORT SUBSTRATE PROVIDED WITH A CHARGE TRAPPING LAYER Download PDF

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Publication number
FR3129028B1
FR3129028B1 FR2111875A FR2111875A FR3129028B1 FR 3129028 B1 FR3129028 B1 FR 3129028B1 FR 2111875 A FR2111875 A FR 2111875A FR 2111875 A FR2111875 A FR 2111875A FR 3129028 B1 FR3129028 B1 FR 3129028B1
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FR
France
Prior art keywords
charge trapping
chamber
base substrate
trapping layer
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2111875A
Other languages
French (fr)
Other versions
FR3129028A1 (en
Inventor
Youngpil Kim
Oleg Kononchuk
Chee Hoe Wong
Chien Shen Kuan
Hoe Tan Seng
Zang Keyan
Ishii Masato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Applied Materials Inc
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR2111875A priority Critical patent/FR3129028B1/en
Priority to PCT/FR2022/052022 priority patent/WO2023084173A1/en
Priority to TW111140922A priority patent/TW202336817A/en
Publication of FR3129028A1 publication Critical patent/FR3129028A1/en
Application granted granted Critical
Publication of FR3129028B1 publication Critical patent/FR3129028B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

L’invention porte sur un procédé de préparation d’un substrat support (1) muni d’une couche de piégeage de charges. Le procédé comprend l’introduction d’un substrat de base (2) en silicium monocristallin présentant une résistivité inférieure ou égale à 500 ohm.cm dans une chambre d’un équipement de dépôt et, sans extraire le substrat de base (2) de la chambre et tout en balayant la chambre à l’aide d’un gaz précurseur, les étapes successives suivantes :- former une couche épitaxiale en silicium intrinsèque (5) sur le substrat de base (2) ; - former une couche diélectrique (3) sur le substrat de base (2) en introduisant dans la chambre un gaz réactif au cours d’une première période de temps ;- former une couche de piégeage de charges (4) en silicium polycristallin directement sur la couche diélectrique (3) en introduisant dans la chambre un gaz précurseur contenant du silicium au cours d’une deuxième période de temps postérieure à la première. La durée pendant laquelle la couche diélectrique (3) est exposée uniquement au gaz porteur, entre la première période de temps et la deuxième période de temps, est inférieure à 30 secondes et la formation de la couche de piégeage de charges (4) est conduite à une température comprise entre 1010°C et 1200°C. Figure à publier avec l’abrégé : -The invention relates to a method for preparing a support substrate (1) provided with a charge trapping layer. The method comprises introducing a base substrate (2) of monocrystalline silicon having a resistivity less than or equal to 500 ohm.cm into a chamber of deposition equipment and, without extracting the base substrate (2) from the chamber and while scanning the chamber using a precursor gas, the following successive steps:- form an epitaxial layer of intrinsic silicon (5) on the base substrate (2); - form a dielectric layer (3) on the base substrate (2) by introducing a reactive gas into the chamber during a first period of time; - form a charge trapping layer (4) of polycrystalline silicon directly on the dielectric layer (3) by introducing a precursor gas containing silicon into the chamber during a second period of time subsequent to the first. The time during which the dielectric layer (3) is exposed only to the carrier gas, between the first time period and the second time period, is less than 30 seconds and the formation of the charge trapping layer (4) is conducted at a temperature between 1010°C and 1200°C. Figure to be published with the abstract: -

FR2111875A 2021-11-09 2021-11-09 METHOD FOR PREPARING A SUPPORT SUBSTRATE PROVIDED WITH A CHARGE TRAPPING LAYER Active FR3129028B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR2111875A FR3129028B1 (en) 2021-11-09 2021-11-09 METHOD FOR PREPARING A SUPPORT SUBSTRATE PROVIDED WITH A CHARGE TRAPPING LAYER
PCT/FR2022/052022 WO2023084173A1 (en) 2021-11-09 2022-10-25 Method for preparing a carrier substrate provided with a charge-trapping layer
TW111140922A TW202336817A (en) 2021-11-09 2022-10-27 Process for preparing a support substrate equipped with a charge-trapping layer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2111875A FR3129028B1 (en) 2021-11-09 2021-11-09 METHOD FOR PREPARING A SUPPORT SUBSTRATE PROVIDED WITH A CHARGE TRAPPING LAYER
FR2111875 2021-11-09

Publications (2)

Publication Number Publication Date
FR3129028A1 FR3129028A1 (en) 2023-05-12
FR3129028B1 true FR3129028B1 (en) 2023-11-10

Family

ID=80786410

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2111875A Active FR3129028B1 (en) 2021-11-09 2021-11-09 METHOD FOR PREPARING A SUPPORT SUBSTRATE PROVIDED WITH A CHARGE TRAPPING LAYER

Country Status (3)

Country Link
FR (1) FR3129028B1 (en)
TW (1) TW202336817A (en)
WO (1) WO2023084173A1 (en)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60041309D1 (en) 1999-03-16 2009-02-26 Shinetsu Handotai Kk METHOD OF MANUFACTURING SILICON WAFER AND SILICON WAFER
FR2838865B1 (en) 2002-04-23 2005-10-14 Soitec Silicon On Insulator PROCESS FOR PRODUCING A SUBSTRATE WITH USEFUL LAYER ON HIGH RESISTIVITY SUPPORT
FR2860341B1 (en) 2003-09-26 2005-12-30 Soitec Silicon On Insulator METHOD FOR MANUFACTURING LOWERED LOWER MULTILAYER STRUCTURE
FR2933233B1 (en) 2008-06-30 2010-11-26 Soitec Silicon On Insulator GOOD RESISTANCE HIGH RESISTIVITY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
FR2953640B1 (en) 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech METHOD FOR MANUFACTURING A SEMICONDUCTOR TYPE STRUCTURE ON INSULATION, WITH REDUCED ELECTRICAL LOSSES AND CORRESPONDING STRUCTURE
FR2973159B1 (en) 2011-03-22 2013-04-19 Soitec Silicon On Insulator METHOD FOR MANUFACTURING BASE SUBSTRATE
FR2985812B1 (en) 2012-01-16 2014-02-07 Soitec Silicon On Insulator METHOD AND DEVICE FOR TESTING SEMICONDUCTOR SUBSTRATES FOR RADIO FREQUENCY APPLICATIONS
US9768056B2 (en) 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
JP6100200B2 (en) 2014-04-24 2017-03-22 信越半導体株式会社 Manufacturing method of bonded SOI wafer
JP6353814B2 (en) * 2015-06-09 2018-07-04 信越半導体株式会社 Manufacturing method of bonded SOI wafer
WO2020008116A1 (en) 2018-07-05 2020-01-09 Soitec Substrate for an integrated radiofrequency device, and process for manufacturing same
FR3104322B1 (en) * 2019-12-05 2023-02-24 Soitec Silicon On Insulator METHOD FOR FORMING A HANDLING SUBSTRATE FOR A COMPOSITE STRUCTURE TARGETING RF APPLICATIONS

Also Published As

Publication number Publication date
WO2023084173A1 (en) 2023-05-19
TW202336817A (en) 2023-09-16
FR3129028A1 (en) 2023-05-12

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