SG11202005826QA - Detachable structure and detachment process using said structure - Google Patents

Detachable structure and detachment process using said structure

Info

Publication number
SG11202005826QA
SG11202005826QA SG11202005826QA SG11202005826QA SG11202005826QA SG 11202005826Q A SG11202005826Q A SG 11202005826QA SG 11202005826Q A SG11202005826Q A SG 11202005826QA SG 11202005826Q A SG11202005826Q A SG 11202005826QA SG 11202005826Q A SG11202005826Q A SG 11202005826QA
Authority
SG
Singapore
Prior art keywords
detachment process
detachable
detachable structure
detachment
Prior art date
Application number
SG11202005826QA
Inventor
Didier Landru
Oleg Kononchuk
Mohamed Nadia Ben
Rénald Guerin
Norbert Colombet
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202005826QA publication Critical patent/SG11202005826QA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
SG11202005826QA 2018-02-13 2019-01-14 Detachable structure and detachment process using said structure SG11202005826QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1851179A FR3077924B1 (en) 2018-02-13 2018-02-13 REMOVABLE STRUCTURE AND DISASSEMBLY METHOD USING THE SAME
PCT/FR2019/050065 WO2019158833A1 (en) 2018-02-13 2019-01-14 Removable structure and removal method using said structure

Publications (1)

Publication Number Publication Date
SG11202005826QA true SG11202005826QA (en) 2020-07-29

Family

ID=62749084

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202005826QA SG11202005826QA (en) 2018-02-13 2019-01-14 Detachable structure and detachment process using said structure

Country Status (8)

Country Link
US (1) US11424156B2 (en)
EP (1) EP3753047B1 (en)
JP (1) JP7275438B2 (en)
CN (1) CN111630653A (en)
FR (1) FR3077924B1 (en)
SG (1) SG11202005826QA (en)
TW (1) TWI762755B (en)
WO (1) WO2019158833A1 (en)

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2756847B1 (en) 1996-12-09 1999-01-08 Commissariat Energie Atomique METHOD FOR SEPARATING AT LEAST TWO ELEMENTS OF A STRUCTURE IN CONTACT WITH THEM BY ION IMPLANTATION
FR2767604B1 (en) * 1997-08-19 2000-12-01 Commissariat Energie Atomique TREATMENT PROCESS FOR MOLECULAR GLUING AND TAKING OFF TWO STRUCTURES
JPH11307747A (en) * 1998-04-17 1999-11-05 Nec Corp Soi substrate and production thereof
JP2002289820A (en) * 2001-03-28 2002-10-04 Nippon Steel Corp Method for manufacturing simox substrate, and simox substrate
JP2004063730A (en) * 2002-07-29 2004-02-26 Shin Etsu Handotai Co Ltd Manufacturing method for soi wafer
JP2004140267A (en) * 2002-10-18 2004-05-13 Semiconductor Energy Lab Co Ltd Semiconductor device and fabrication method thereof
FR2865574B1 (en) * 2004-01-26 2006-04-07 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A DEMOUNTABLE SUBSTRATE
JP4319078B2 (en) * 2004-03-26 2009-08-26 シャープ株式会社 Manufacturing method of semiconductor device
JP2007220749A (en) * 2006-02-14 2007-08-30 Seiko Epson Corp Method of manufacturing semiconductor device
FR2898430B1 (en) * 2006-03-13 2008-06-06 Soitec Silicon On Insulator METHOD FOR PRODUCING A STRUCTURE COMPRISING AT LEAST ONE THIN LAYER OF AMORPHOUS MATERIAL OBTAINED BY EPITAXIA ON A SUPPORT SUBSTRATE AND STRUCTURE OBTAINED ACCORDING TO SAID METHOD
FR2898431B1 (en) * 2006-03-13 2008-07-25 Soitec Silicon On Insulator METHOD FOR MANUFACTURING THIN FILM
FR2905801B1 (en) * 2006-09-12 2008-12-05 Soitec Silicon On Insulator METHOD FOR TRANSFERRING A HIGH TEMPERATURE LAYER
CN101960604B (en) * 2008-03-13 2013-07-10 S.O.I.Tec绝缘体上硅技术公司 Substrate having a charged zone in an insulating buried layer
CN102460642A (en) 2009-06-24 2012-05-16 株式会社半导体能源研究所 Method for reprocessing semiconductor substrate and method for manufacturing soi substrate
JP5917036B2 (en) * 2010-08-05 2016-05-11 株式会社半導体エネルギー研究所 Method for manufacturing SOI substrate
JP6213046B2 (en) 2013-08-21 2017-10-18 信越半導体株式会社 Manufacturing method of bonded wafer
JP6516957B2 (en) 2013-09-04 2019-05-22 株式会社Sumco Method of manufacturing epitaxial wafer and method of manufacturing bonded wafer
JP6544807B2 (en) 2014-06-03 2019-07-17 株式会社日本製鋼所 Method of manufacturing semiconductor having gettering layer, method of manufacturing semiconductor device, and semiconductor device
WO2016081313A1 (en) * 2014-11-18 2016-05-26 Sunedison Semiconductor Limited A method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers

Also Published As

Publication number Publication date
FR3077924A1 (en) 2019-08-16
US20210050249A1 (en) 2021-02-18
FR3077924B1 (en) 2020-01-17
EP3753047B1 (en) 2022-10-05
US11424156B2 (en) 2022-08-23
TW201935519A (en) 2019-09-01
EP3753047A1 (en) 2020-12-23
JP7275438B2 (en) 2023-05-18
TWI762755B (en) 2022-05-01
JP2021513735A (en) 2021-05-27
CN111630653A (en) 2020-09-04
WO2019158833A1 (en) 2019-08-22

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