SG11201907886QA - Nonvolatile semiconductor storage device - Google Patents

Nonvolatile semiconductor storage device

Info

Publication number
SG11201907886QA
SG11201907886QA SG11201907886QA SG11201907886QA SG 11201907886Q A SG11201907886Q A SG 11201907886QA SG 11201907886Q A SG11201907886Q A SG 11201907886QA SG 11201907886Q A SG11201907886Q A SG 11201907886QA
Authority
SG
Singapore
Prior art keywords
bit line
reading bit
adjacent
compared
volatile semiconductor
Prior art date
Application number
Inventor
Shinji Yoshida
Kazumasa Yanagisawa
Shuichi Sato
Yasuhiro Taniguchi
Original Assignee
Floadia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Floadia Corp filed Critical Floadia Corp
Publication of SG11201907886QA publication Critical patent/SG11201907886QA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

A non-volatile semiconductor memory device that achieves downsizing as compared to conventional cases is disclosed. A non-volatile semiconductor memory device 1 has a configuration in which a memory cell 3a (3b) is disposed between a programming bit line PGP0 (PGP1) and a reading bit line BLP. The reading bit line BLP provided between the memory cells 3a and 3b adjacent to each other is shared by the memory cells 3a and 3b adjacent to each other. This configuration of the non-volatile semiconductor memory device 1, in which the reading bit line BLP is shared by the memory cells 3a and 3b adjacent to each other, leads to reduction of the number of reading bit lines as compared to that in a conventional configuration, and further leads to reduction of the area of a control circuit and a sense amplifier circuit connected with the reading bit line, thereby achieving downsizing as compared to conventional cases accordingly.
SG11201907886Q 2017-03-24 2018-02-05 Nonvolatile semiconductor storage device SG11201907886QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017059316A JP6276447B1 (en) 2017-03-24 2017-03-24 Nonvolatile semiconductor memory device
PCT/JP2018/003794 WO2018173513A1 (en) 2017-03-24 2018-02-05 Nonvolatile semiconductor storage device

Publications (1)

Publication Number Publication Date
SG11201907886QA true SG11201907886QA (en) 2019-10-30

Family

ID=61158423

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201907886Q SG11201907886QA (en) 2017-03-24 2018-02-05 Nonvolatile semiconductor storage device

Country Status (8)

Country Link
US (1) US11127469B2 (en)
JP (1) JP6276447B1 (en)
KR (1) KR102540105B1 (en)
CN (1) CN110419080B (en)
IL (1) IL269012B2 (en)
SG (1) SG11201907886QA (en)
TW (1) TWI660354B (en)
WO (1) WO2018173513A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10692557B1 (en) 2019-04-11 2020-06-23 Micron Technology, Inc. Reference voltage management
CN111402943B (en) * 2020-06-02 2020-09-04 深圳市芯天下技术有限公司 Method, system, storage medium and terminal for reducing area of read operation pump of non-flash memory
US11069743B1 (en) * 2020-06-09 2021-07-20 Globalfoundries Singapore Pte. Ltd. Non-volatile memory elements with a multi-level cell configuration

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2554620B2 (en) * 1985-12-12 1996-11-13 株式会社東芝 Nonvolatile semiconductor memory device
US6903964B2 (en) * 2002-06-28 2005-06-07 Freescale Semiconductor, Inc. MRAM architecture with electrically isolated read and write circuitry
JP2005175411A (en) 2003-12-12 2005-06-30 Genusion:Kk Semiconductor device and its manufacturing method
JP2006031795A (en) * 2004-07-14 2006-02-02 Renesas Technology Corp Nonvolatile semiconductor memory
JP4683995B2 (en) * 2005-04-28 2011-05-18 ルネサスエレクトロニクス株式会社 Nonvolatile semiconductor memory device
JP4800109B2 (en) 2005-09-13 2011-10-26 ルネサスエレクトロニクス株式会社 Semiconductor device
US7391647B2 (en) * 2006-04-11 2008-06-24 Mosys, Inc. Non-volatile memory in CMOS logic process and method of operation thereof
JP5556873B2 (en) * 2012-10-19 2014-07-23 株式会社フローディア Nonvolatile semiconductor memory device
JP6069137B2 (en) * 2013-09-04 2017-02-01 株式会社フローディア Nonvolatile semiconductor memory device
KR20150054225A (en) 2013-11-11 2015-05-20 삼성전자주식회사 Logic embedded non-volatile memory device
JP6235901B2 (en) 2013-12-27 2017-11-22 ルネサスエレクトロニクス株式会社 Semiconductor device
JP6280428B2 (en) * 2014-04-18 2018-02-14 株式会社フローディア Nonvolatile semiconductor memory device
KR102554495B1 (en) * 2016-01-22 2023-07-12 에스케이하이닉스 주식회사 Nonvolatile memory cell having lateral coupling structure and memory cell array using the nonvolatile memory cell

Also Published As

Publication number Publication date
KR102540105B1 (en) 2023-06-08
TWI660354B (en) 2019-05-21
JP6276447B1 (en) 2018-02-07
TW201835925A (en) 2018-10-01
CN110419080B (en) 2023-06-20
IL269012B1 (en) 2023-08-01
US20200075105A1 (en) 2020-03-05
IL269012A (en) 2019-10-31
IL269012B2 (en) 2023-12-01
KR20190130465A (en) 2019-11-22
CN110419080A (en) 2019-11-05
JP2018163711A (en) 2018-10-18
US11127469B2 (en) 2021-09-21
WO2018173513A1 (en) 2018-09-27

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