SG11201805988VA - Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches - Google Patents

Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches

Info

Publication number
SG11201805988VA
SG11201805988VA SG11201805988VA SG11201805988VA SG11201805988VA SG 11201805988V A SG11201805988V A SG 11201805988VA SG 11201805988V A SG11201805988V A SG 11201805988VA SG 11201805988V A SG11201805988V A SG 11201805988VA SG 11201805988V A SG11201805988V A SG 11201805988VA
Authority
SG
Singapore
Prior art keywords
dram
cache
memory
dram cache
international
Prior art date
Application number
SG11201805988VA
Other languages
English (en)
Inventor
Natarajan Vaidhyanathan
Mattheus Heddes
Colin Verrilli
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SG11201805988VA publication Critical patent/SG11201805988VA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1008—Correctness of operation, e.g. memory ordering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/281—Single cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/70—Details relating to dynamic memory management
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
SG11201805988VA 2016-02-22 2017-02-01 Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches SG11201805988VA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662298088P 2016-02-22 2016-02-22
US15/228,320 US10176096B2 (en) 2016-02-22 2016-08-04 Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches
PCT/US2017/016005 WO2017146882A1 (en) 2016-02-22 2017-02-01 Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches

Publications (1)

Publication Number Publication Date
SG11201805988VA true SG11201805988VA (en) 2018-09-27

Family

ID=59629409

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201805988VA SG11201805988VA (en) 2016-02-22 2017-02-01 Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches

Country Status (11)

Country Link
US (1) US10176096B2 (es)
EP (1) EP3420460B1 (es)
JP (1) JP2019509557A (es)
KR (1) KR20180113536A (es)
CN (1) CN108701093A (es)
BR (1) BR112018017135A2 (es)
ES (1) ES2870516T3 (es)
HK (1) HK1256013A1 (es)
SG (1) SG11201805988VA (es)
TW (1) TW201732599A (es)
WO (1) WO2017146882A1 (es)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10783083B2 (en) * 2018-02-12 2020-09-22 Stmicroelectronics (Beijing) Research & Development Co. Ltd Cache management device, system and method
CN109669882B (zh) * 2018-12-28 2021-03-09 贵州华芯通半导体技术有限公司 带宽感知的动态高速缓存替换方法、装置、系统和介质

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2256512B (en) 1991-06-04 1995-03-15 Intel Corp Second level cache controller unit and system
US5414827A (en) * 1991-12-19 1995-05-09 Opti, Inc. Automatic cache flush
US6029224A (en) * 1995-06-07 2000-02-22 Lucent Technologies Inc. Self-contained memory apparatus having diverse types of memory and distributed control
US6173368B1 (en) * 1995-12-18 2001-01-09 Texas Instruments Incorporated Class categorized storage circuit for storing non-cacheable data until receipt of a corresponding terminate signal
US5752262A (en) * 1996-07-25 1998-05-12 Vlsi Technology System and method for enabling and disabling writeback cache
US6092155A (en) * 1997-07-10 2000-07-18 International Business Machines Corporation Cache coherent network adapter for scalable shared memory processing systems
US6327645B1 (en) * 1999-11-08 2001-12-04 Silicon Integrated Systems Corp. Cache memory system with memory request address queue, cache write address queue, and cache read address queue
US7146454B1 (en) * 2002-04-16 2006-12-05 Cypress Semiconductor Corporation Hiding refresh in 1T-SRAM architecture
US20030204702A1 (en) * 2002-04-30 2003-10-30 Adc Dsl Systems, Inc. Flexible memory architecture for an embedded processor
JP3953903B2 (ja) * 2002-06-28 2007-08-08 富士通株式会社 キャッシュメモリ装置、及び、参照履歴のビット誤り検出方法
US20040225881A1 (en) 2002-12-02 2004-11-11 Walmsley Simon Robert Variant keys
US6880047B2 (en) * 2003-03-28 2005-04-12 Emulex Design & Manufacturing Corporation Local emulation of data RAM utilizing write-through cache hardware within a CPU module
US7613870B2 (en) * 2004-11-18 2009-11-03 International Business Machines Corporation Efficient memory usage in systems including volatile and high-density memories
US7958312B2 (en) 2005-11-15 2011-06-07 Oracle America, Inc. Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state
US8593474B2 (en) * 2005-12-30 2013-11-26 Intel Corporation Method and system for symmetric allocation for a shared L2 mapping cache
GB2458295B (en) * 2008-03-12 2012-01-11 Advanced Risc Mach Ltd Cache accessing using a micro tag
US8799582B2 (en) * 2008-12-30 2014-08-05 Intel Corporation Extending cache coherency protocols to support locally buffered data
EP2441005A2 (en) 2009-06-09 2012-04-18 Martin Vorbach System and method for a cache in a multi-core processor
WO2013095537A1 (en) * 2011-12-22 2013-06-27 Intel Corporation Controlling a processor cache using a real-time attribute
WO2013095639A1 (en) 2011-12-23 2013-06-27 Intel Corporation Utility and lifetime based cache replacement policy
US9286221B1 (en) * 2012-06-06 2016-03-15 Reniac, Inc. Heterogeneous memory system
US8819342B2 (en) * 2012-09-26 2014-08-26 Qualcomm Incorporated Methods and apparatus for managing page crossing instructions with different cacheability
US9348753B2 (en) * 2012-10-10 2016-05-24 Advanced Micro Devices, Inc. Controlling prefetch aggressiveness based on thrash events
US20150095582A1 (en) * 2013-09-30 2015-04-02 Avaya, Inc. Method for Specifying Packet Address Range Cacheability
WO2015152857A1 (en) 2014-03-29 2015-10-08 Empire Technology Development Llc Energy-efficient dynamic dram cache sizing
US20150293847A1 (en) * 2014-04-13 2015-10-15 Qualcomm Incorporated Method and apparatus for lowering bandwidth and power in a cache using read with invalidate
US9356602B1 (en) * 2015-05-14 2016-05-31 Xilinx, Inc. Management of memory resources in a programmable integrated circuit

Also Published As

Publication number Publication date
US20170242793A1 (en) 2017-08-24
ES2870516T3 (es) 2021-10-27
EP3420460A1 (en) 2019-01-02
CN108701093A (zh) 2018-10-23
TW201732599A (zh) 2017-09-16
HK1256013A1 (zh) 2019-09-13
BR112018017135A2 (pt) 2019-01-02
KR20180113536A (ko) 2018-10-16
EP3420460B1 (en) 2021-04-07
US10176096B2 (en) 2019-01-08
JP2019509557A (ja) 2019-04-04
WO2017146882A1 (en) 2017-08-31

Similar Documents

Publication Publication Date Title
SG11201907532VA (en) Active boundary quilt architecture memory
SG11201908071PA (en) Persistent memory for key-value storage
SG11201811426UA (en) Distributed electronic record and transaction history
SG11201903107SA (en) Method and system for providing information of stored object
SG11201903787YA (en) Exploiting input data sparsity in neural network compute units
SG11201907679TA (en) Business verification method and apparatus
SG11201811095UA (en) Multi-level storage in ferroelectric memory
SG11201906794TA (en) Systems and methods for issuing and tracking digital tokens within distributed network nodes
SG11201909950QA (en) Identifying entities in electronic medical records
SG11201908554PA (en) Methods and devices for acquiring and recording tracking information on blockchain
SG11201806404SA (en) Systems and methods for storing and sharing transactional data using distributed computer systems
SG11201909943SA (en) System and method for high accuracy location determination and parking
SG11201906834SA (en) Achieving consensus among network nodes in a distributed system
SG11201908451UA (en) Method, apparatus, and system for blockchain consensus
SG11201907320YA (en) Trusted login method, server, and system
SG11201909630TA (en) Anti-replay attack authentication protocol
SG11201906755VA (en) Digital certificate management method, apparatus, and system
SG11201908959SA (en) Digital asset account management
SG11201809795VA (en) Memory access techniques in memory devices with multiple partitions
SG11201900816TA (en) A hybrid memory device
SG11201804536QA (en) Method and system for communication in instant messaging application
SG11201906869UA (en) Express package delivery through recipient location detection
SG11201806650VA (en) Systems and methods for providing a personal distributed ledger
SG11201807821SA (en) Information presentation method, apparatus, and system based on electronic waybill
SG11201906827XA (en) Shared secret-based blockchain storage